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| author | Selene ToyKeeper | 2022-04-14 21:32:08 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2022-04-14 21:32:08 -0600 |
| commit | 30a503f84b80cef1a46ecbd33bfd4afd16e08e39 (patch) | |
| tree | 760140f35e4377f9eecc0c740f9e78afe6dbf0b1 | |
| parent | sp10-pro: hard reset phase while turning off, fixes shutoff bug without a delay (diff) | |
| download | anduril-30a503f84b80cef1a46ecbd33bfd4afd16e08e39.tar.gz anduril-30a503f84b80cef1a46ecbd33bfd4afd16e08e39.tar.bz2 anduril-30a503f84b80cef1a46ecbd33bfd4afd16e08e39.zip | |
applied new phase-hack flags to other builds where relevant
Diffstat (limited to '')
| -rw-r--r-- | hwdef-BLF_LT1.h | 3 | ||||
| -rw-r--r-- | hwdef-Emisar_D4Sv2-tintramp.h | 3 | ||||
| -rw-r--r-- | hwdef-Noctigon_DM11-12V.h | 3 | ||||
| -rw-r--r-- | hwdef-Noctigon_DM11-SBT90.h | 3 | ||||
| -rw-r--r-- | hwdef-Noctigon_DM11.h | 3 | ||||
| -rw-r--r-- | hwdef-Noctigon_KR4-12V.h | 3 | ||||
| -rw-r--r-- | hwdef-Noctigon_KR4.h | 3 |
7 files changed, 21 insertions, 0 deletions
diff --git a/hwdef-BLF_LT1.h b/hwdef-BLF_LT1.h index 16e1c90..4e81c42 100644 --- a/hwdef-BLF_LT1.h +++ b/hwdef-BLF_LT1.h @@ -20,6 +20,9 @@ // dynamic PWM with tint ramping (not supported on attiny85) //#define USE_DYN_PWM // dynamic frequency and speed //#define PWM1_CNT TCNT0 // for dynamic PWM, reset phase +//#define PWM1_PHASE_RESET_OFF // force reset while shutting off +//#define PWM1_PHASE_RESET_ON // force reset while turning on +//#define PWM1_PHASE_SYNC // manual sync while changing level // usually PWM1_LVL would be a hardware register, but we need to abstract // it out to a soft brightness value, in order to handle tint ramping diff --git a/hwdef-Emisar_D4Sv2-tintramp.h b/hwdef-Emisar_D4Sv2-tintramp.h index 90545f4..0f4a77a 100644 --- a/hwdef-Emisar_D4Sv2-tintramp.h +++ b/hwdef-Emisar_D4Sv2-tintramp.h @@ -65,6 +65,9 @@ uint16_t PWM1_LVL; #define PWM1_PIN PB3 // pin 16, Opamp reference #define TINT1_LVL OCR1A // OCR1A is the output compare register for PB3 #define PWM1_CNT TCNT1 // for dynamic PWM, reset phase +#define PWM1_PHASE_RESET_OFF // force reset while shutting off +#define PWM1_PHASE_RESET_ON // force reset while turning on +#define PWM1_PHASE_SYNC // manual sync while changing level // gah, this driver is weird... // two linear channels are treated as one, diff --git a/hwdef-Noctigon_DM11-12V.h b/hwdef-Noctigon_DM11-12V.h index bd24768..a0d9715 100644 --- a/hwdef-Noctigon_DM11-12V.h +++ b/hwdef-Noctigon_DM11-12V.h @@ -61,6 +61,9 @@ #define PWM1_PIN PB3 // pin 16, Opamp reference #define PWM1_LVL OCR1A // OCR1A is the output compare register for PB3 #define PWM1_CNT TCNT1 // for dynamic PWM, reset phase +#define PWM1_PHASE_RESET_OFF // force reset while shutting off +#define PWM1_PHASE_RESET_ON // force reset while turning on +#define PWM1_PHASE_SYNC // manual sync while changing level // PWM parameters of both channels are tied together because they share a counter #define PWM1_TOP ICR1 // holds the TOP value for for variable-resolution PWM diff --git a/hwdef-Noctigon_DM11-SBT90.h b/hwdef-Noctigon_DM11-SBT90.h index 64ebe05..8d7aa3d 100644 --- a/hwdef-Noctigon_DM11-SBT90.h +++ b/hwdef-Noctigon_DM11-SBT90.h @@ -56,6 +56,9 @@ #define PWM1_PIN PB3 // pin 16, Opamp reference #define PWM1_LVL OCR1A // OCR1A is the output compare register for PB3 #define PWM1_CNT TCNT1 // for dynamic PWM, reset phase +#define PWM1_PHASE_RESET_OFF // force reset while shutting off +#define PWM1_PHASE_RESET_ON // force reset while turning on +#define PWM1_PHASE_SYNC // manual sync while changing level #define PWM2_PIN PA6 // pin 1, DD FET PWM #define PWM2_LVL OCR1B // OCR1B is the output compare register for PA6 diff --git a/hwdef-Noctigon_DM11.h b/hwdef-Noctigon_DM11.h index 19532e9..ea51432 100644 --- a/hwdef-Noctigon_DM11.h +++ b/hwdef-Noctigon_DM11.h @@ -55,6 +55,9 @@ #define PWM1_PIN PB3 // pin 16, Opamp reference #define PWM1_LVL OCR1A // OCR1A is the output compare register for PB3 #define PWM1_CNT TCNT1 // for dynamic PWM, reset phase +#define PWM1_PHASE_RESET_OFF // force reset while shutting off +#define PWM1_PHASE_RESET_ON // force reset while turning on +#define PWM1_PHASE_SYNC // manual sync while changing level #define PWM2_PIN PA6 // pin 1, DD FET PWM #define PWM2_LVL OCR1B // OCR1B is the output compare register for PA6 diff --git a/hwdef-Noctigon_KR4-12V.h b/hwdef-Noctigon_KR4-12V.h index 20724a2..e6cf18a 100644 --- a/hwdef-Noctigon_KR4-12V.h +++ b/hwdef-Noctigon_KR4-12V.h @@ -55,6 +55,9 @@ #define PWM1_PIN PB3 // pin 16, Opamp reference #define PWM1_LVL OCR1A // OCR1A is the output compare register for PB3 #define PWM1_CNT TCNT1 // for dynamic PWM, reset phase +#define PWM1_PHASE_RESET_OFF // force reset while shutting off +#define PWM1_PHASE_RESET_ON // force reset while turning on +#define PWM1_PHASE_SYNC // manual sync while changing level // PWM parameters of both channels are tied together because they share a counter #define PWM1_TOP ICR1 // holds the TOP value for for variable-resolution PWM diff --git a/hwdef-Noctigon_KR4.h b/hwdef-Noctigon_KR4.h index 75dd4c6..487d3ac 100644 --- a/hwdef-Noctigon_KR4.h +++ b/hwdef-Noctigon_KR4.h @@ -60,6 +60,9 @@ #define PWM1_PIN PB3 // pin 16, Opamp reference #define PWM1_LVL OCR1A // OCR1A is the output compare register for PB3 #define PWM1_CNT TCNT1 // for dynamic PWM, reset phase +#define PWM1_PHASE_RESET_OFF // force reset while shutting off +#define PWM1_PHASE_RESET_ON // force reset while turning on +#define PWM1_PHASE_SYNC // manual sync while changing level #define PWM2_PIN PA6 // pin 1, DD FET PWM #define PWM2_LVL OCR1B // OCR1B is the output compare register for PA6 |