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| author | Selene ToyKeeper | 2015-10-05 18:09:06 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2015-10-05 18:09:06 -0600 |
| commit | 116b84f659773647333bed942bd5ce5bd96752c2 (patch) | |
| tree | bc6f7d2ba35c3915512a9aec65727ddb2530c4d9 | |
| parent | merged tiny25 branch (diff) | |
| download | anduril-116b84f659773647333bed942bd5ce5bd96752c2.tar.gz anduril-116b84f659773647333bed942bd5ce5bd96752c2.tar.bz2 anduril-116b84f659773647333bed942bd5ce5bd96752c2.zip | |
Added nanjg board/pin layout definition to tk-attiny.h.
(at least works for s7.c, haven't tried others yet)
Diffstat (limited to '')
| -rw-r--r-- | tk-attiny.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tk-attiny.h b/tk-attiny.h index 9415a97..4fee640 100644 --- a/tk-attiny.h +++ b/tk-attiny.h @@ -84,6 +84,19 @@ // TODO: fill in this section, update Ferrero_Rocher code to use it. #endif // FERRERO_ROCHER_LAYOUT +#ifdef NANJG_LAYOUT +#define STAR2_PIN PB0 +#define STAR3_PIN PB4 +#define STAR4_PIN PB3 +#define PWM_PIN PB1 +#define VOLTAGE_PIN PB2 +#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2 +#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2 +#define ADC_PRSCL 0x06 // clk/64 + +#define PWM_LVL OCR0B // OCR0B is the output compare register for PB1 +#endif // NANJG_LAYOUT + #ifndef PWM_LVL Hey, you need to define an I/O pin layout. #endif |