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| author | Gabriel Hart | 2021-08-12 11:15:48 -0500 |
|---|---|---|
| committer | Gabriel Hart | 2021-08-12 11:15:48 -0500 |
| commit | 1d3a4d7996ca5b046287f28db145eb3d09c9c495 (patch) | |
| tree | 91aa3228f2781f9e43b2ee0f721778db9678ccce /hw | |
| parent | Finalized SP10S and renamed to SP10 Pro. Updated Sofirn settings to include SOS. (diff) | |
| parent | got PFM / dynamic PWM actually working on Noctigon KR4 (diff) | |
| download | anduril-1d3a4d7996ca5b046287f28db145eb3d09c9c495.tar.gz anduril-1d3a4d7996ca5b046287f28db145eb3d09c9c495.tar.bz2 anduril-1d3a4d7996ca5b046287f28db145eb3d09c9c495.zip | |
Merge updates from TKs main branch
Diffstat (limited to '')
| -rw-r--r-- | hwdef-Noctigon_KR4.h | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/hwdef-Noctigon_KR4.h b/hwdef-Noctigon_KR4.h index feb49e6..eee4e08 100644 --- a/hwdef-Noctigon_KR4.h +++ b/hwdef-Noctigon_KR4.h @@ -41,8 +41,9 @@ #include <avr/io.h> #define PWM_CHANNELS 2 -#define PWM_BITS 10 // 0 to 1023 at 4 kHz, not 0 to 255 at 16 kHz -#define PWM_TOP 1023 +#define PWM_BITS 16 // data type needs 16 bits, not 8 +#define PWM_TOP 255 // highest value used in top half of ramp +#define USE_DYN_PWM // dynamic frequency and speed #define SWITCH_PIN PB2 // pin 17 #define SWITCH_PCINT PCINT10 // pin 17 pin change interrupt @@ -58,10 +59,14 @@ #define PWM1_PIN PB3 // pin 16, Opamp reference #define PWM1_LVL OCR1A // OCR1A is the output compare register for PB3 +#define PWM1_CNT TCNT1 // for dynamic PWM, reset phase #define PWM2_PIN PA6 // pin 1, DD FET PWM #define PWM2_LVL OCR1B // OCR1B is the output compare register for PA6 +// PWM parameters of both channels are tied together because they share a counter +#define PWM1_TOP ICR1 // holds the TOP value for for variable-resolution PWM + #define LED_ENABLE_PIN PB0 // pin 19, Opamp power #define LED_ENABLE_PORT PORTB // control port for PB0 @@ -131,14 +136,17 @@ inline void hwdef_setup() { // CS1[2:0]: 0,0,1: clk/1 (No prescaling) (DS table 12-6) // COM1A[1:0]: 1,0: PWM OC1A in the normal direction (DS table 12-4) // COM1B[1:0]: 1,0: PWM OC1B in the normal direction (DS table 12-4) - TCCR1A = (1<<WGM11) | (1<<WGM10) // 10-bit (TOP=0x03FF) (DS table 12-5) + TCCR1A = (1<<WGM11) | (0<<WGM10) // adjustable PWM (TOP=ICR1) (DS table 12-5) | (1<<COM1A1) | (0<<COM1A0) // PWM 1A in normal direction (DS table 12-4) | (1<<COM1B1) | (0<<COM1B0) // PWM 1B in normal direction (DS table 12-4) ; TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6) - | (0<<WGM13) | (0<<WGM12) // phase-correct PWM (DS table 12-5) + | (1<<WGM13) | (0<<WGM12) // phase-correct adjustable PWM (DS table 12-5) ; + // set PWM resolution + PWM1_TOP = PWM_TOP; + // set up e-switch //PORTB = (1 << SWITCH_PIN); // TODO: configure PORTA / PORTB / PORTC? PUEB = (1 << SWITCH_PIN); // pull-up for e-switch |