merged updates from fsm branch, including RampingIOS V3 and Werner UIs...

... plus a bunch of other updates, fixes, improvements, etc.

12 files changed, 270 insertions, 0 deletions

diff --git a/hwdef-BLF_GT.h b/hwdef-BLF_GT.h
new file mode 100644
index 0000000..1a05741
--- /dev/null
+++ b/hwdef-BLF_GT.h
@@ -0,0 +1,40 @@
+/* BLF GT driver layout
+ *           ----
+ *   Reset -|1  8|- VCC (unused)
+ * eswitch -|2  7|- Voltage divider
+ * AUX LED -|3  6|- Current control (buck level)
+ *     GND -|4  5|- PWM (buck output on/off)
+ *           ----
+ */
+
+#define PWM_CHANNELS 2
+
+#define AUXLED_PIN   PB4    // pin 3
+
+#define SWITCH_PIN   PB3    // pin 2
+#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt
+
+#define PWM1_PIN PB0        // pin 5, 1x7135 PWM
+#define PWM1_LVL OCR0A      // OCR0A is the output compare register for PB0
+#define PWM2_PIN PB1        // pin 6, FET PWM
+#define PWM2_LVL OCR0B      // OCR0B is the output compare register for PB1
+
+#define USE_VOLTAGE_DIVIDER // use a voltage divider on pin 7, not VCC
+#define VOLTAGE_PIN PB2     // pin 7, voltage ADC
+#define VOLTAGE_CHANNEL 0x01 // MUX 01 corresponds with PB2
+// 1.1V reference, left-adjust, ADC1/PB2
+//#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | (1 << ADLAR) | VOLTAGE_CHANNEL)
+// 1.1V reference, no left-adjust, ADC1/PB2
+#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL)
+#define VOLTAGE_ADC_DIDR    ADC1D   // Digital input disable bit corresponding with PB2
+#define ADC_PRSCL   0x06    // clk/64
+
+// Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line)
+#define ADC_44 184
+#define ADC_22 92
+
+#define TEMP_CHANNEL 0b00001111
+
+#define FAST 0xA3           // fast PWM both channels
+#define PHASE 0xA1          // phase-correct PWM both channels
+
diff --git a/hwdef-BLF_Q8.h b/hwdef-BLF_Q8.h
new file mode 100644
index 0000000..f00c392
--- /dev/null
+++ b/hwdef-BLF_Q8.h
@@ -0,0 +1,16 @@
+/* BLF Q8 driver layout
+ */
+// Q8 driver is the same as a D4, basically
+#include "hwdef-Emisar_D4.h"
+
+// ... except the Q8 has a lighted button
+#ifndef AUXLED_PIN
+#define AUXLED_PIN   PB4    // pin 3
+#endif
+
+// average drop across diode on this hardware
+#ifdef VOLTAGE_FUDGE_FACTOR
+#undef VOLTAGE_FUDGE_FACTOR
+#endif
+#define VOLTAGE_FUDGE_FACTOR 7  // add 0.35V
+
diff --git a/hwdef-Emisar_D1.h b/hwdef-Emisar_D1.h
new file mode 100644
index 0000000..6df8705
--- /dev/null
+++ b/hwdef-Emisar_D1.h
@@ -0,0 +1,4 @@
+/* Emisar D1 driver layout
+ */
+// D1 driver is exactly the same as a D4
+#include "hwdef-Emisar_D4.h"
diff --git a/hwdef-Emisar_D1S.h b/hwdef-Emisar_D1S.h
new file mode 100644
index 0000000..31792c7
--- /dev/null
+++ b/hwdef-Emisar_D1S.h
@@ -0,0 +1,4 @@
+/* Emisar D1S driver layout
+ */
+// D1S driver is exactly the same as a D4
+#include "hwdef-Emisar_D4.h"
diff --git a/hwdef-Emisar_D4.h b/hwdef-Emisar_D4.h
new file mode 100644
index 0000000..105d3b9
--- /dev/null
+++ b/hwdef-Emisar_D4.h
@@ -0,0 +1,36 @@
+/* Emisar D4 driver layout
+ *           ----
+ *   Reset -|1  8|- VCC
+ * eswitch -|2  7|-
+ * AUX LED -|3  6|- PWM (FET)
+ *     GND -|4  5|- PWM (1x7135)
+ *           ----
+ */
+
+#define PWM_CHANNELS 2
+
+#define AUXLED_PIN   PB4    // pin 3
+
+#define SWITCH_PIN   PB3    // pin 2
+#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt
+
+#define PWM1_PIN PB0        // pin 5, 1x7135 PWM
+#define PWM1_LVL OCR0A      // OCR0A is the output compare register for PB0
+#define PWM2_PIN PB1        // pin 6, FET PWM
+#define PWM2_LVL OCR0B      // OCR0B is the output compare register for PB1
+
+// (FIXME: remove?  not used?)
+#define VOLTAGE_PIN PB2     // pin 7, voltage ADC
+#define ADC_CHANNEL 0x01    // MUX 01 corresponds with PB2
+#define ADC_DIDR    ADC1D   // Digital input disable bit corresponding with PB2
+#define ADC_PRSCL   0x06    // clk/64
+
+// average drop across diode on this hardware
+#define VOLTAGE_FUDGE_FACTOR 5  // add 0.25V
+
+//#define TEMP_DIDR   ADC4D
+#define TEMP_CHANNEL 0b00001111
+
+#define FAST 0xA3           // fast PWM both channels
+#define PHASE 0xA1          // phase-correct PWM both channels
+
diff --git a/hwdef-Emisar_D4S.h b/hwdef-Emisar_D4S.h
new file mode 100644
index 0000000..47ef1eb
--- /dev/null
+++ b/hwdef-Emisar_D4S.h
@@ -0,0 +1,10 @@
+/* Emisar D4S driver layout
+ */
+// same as a D4, basically
+#include "hwdef-Emisar_D4.h"
+
+// ... except the D4S has aux LEDs under the optic
+#ifndef AUXLED_PIN
+#define AUXLED_PIN   PB4    // pin 3
+#endif
+
diff --git a/hwdef-FET_7135.h b/hwdef-FET_7135.h
new file mode 100644
index 0000000..58df7b2
--- /dev/null
+++ b/hwdef-FET_7135.h
@@ -0,0 +1,32 @@
+/* FET + 7135 driver layout
+ *           ----
+ *   Reset -|1  8|- VCC
+ *     OTC -|2  7|- Voltage ADC
+ *  Star 3 -|3  6|- PWM (FET)
+ *     GND -|4  5|- PWM (1x7135)
+ *           ----
+ */
+
+#define STAR2_PIN   PB0     // If this pin isn't used for ALT_PWM
+#define STAR3_PIN   PB4     // pin 3
+
+#define CAP_PIN     PB3     // pin 2, OTC
+#define CAP_CHANNEL 0x03    // MUX 03 corresponds with PB3 (Star 4)
+#define CAP_DIDR    ADC3D   // Digital input disable bit corresponding with PB3
+
+#define PWM_PIN     PB1     // pin 6, FET PWM
+#define PWM_LVL     OCR0B   // OCR0B is the output compare register for PB1
+#define ALT_PWM_PIN PB0     // pin 5, 1x7135 PWM
+#define ALT_PWM_LVL OCR0A   // OCR0A is the output compare register for PB0
+
+#define VOLTAGE_PIN PB2     // pin 7, voltage ADC
+#define ADC_CHANNEL 0x01    // MUX 01 corresponds with PB2
+#define ADC_DIDR    ADC1D   // Digital input disable bit corresponding with PB2
+#define ADC_PRSCL   0x06    // clk/64
+
+//#define TEMP_DIDR   ADC4D
+#define TEMP_CHANNEL 0b00001111
+
+#define FAST 0xA3           // fast PWM both channels
+#define PHASE 0xA1          // phase-correct PWM both channels
+
diff --git a/hwdef-FW3A.h b/hwdef-FW3A.h
new file mode 100644
index 0000000..5e253c7
--- /dev/null
+++ b/hwdef-FW3A.h
@@ -0,0 +1,35 @@
+/* BLF/TLF FW3A driver layout
+ *           ----
+ *   Reset -|1  8|- VCC
+ * eswitch -|2  7|- optic nerve
+ *     FET -|3  6|- 7x7135
+ *     GND -|4  5|- 1x7135
+ *           ----
+ */
+
+#define PWM_CHANNELS 3
+
+#define SWITCH_PIN   PB3    // pin 2
+#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt
+
+#define PWM1_PIN PB0        // pin 5, 1x7135 PWM
+#define PWM1_LVL OCR0A      // OCR0A is the output compare register for PB0
+#define PWM2_PIN PB1        // pin 6, FET PWM
+#define PWM2_LVL OCR0B      // OCR0B is the output compare register for PB1
+#define PWM3_PIN PB4        // pin 3
+#define PWM3_LVL OCR1B
+
+#define VISION_PIN PB2      // pin 7, optic nerve
+#define ADC_CHANNEL 0x01    // MUX 01 corresponds with PB2
+#define ADC_DIDR    ADC1D   // Digital input disable bit corresponding with PB2
+#define ADC_PRSCL   0x06    // clk/64
+
+// average drop across diode on this hardware
+#define VOLTAGE_FUDGE_FACTOR 5  // add 0.25V
+
+//#define TEMP_DIDR   ADC4D
+#define TEMP_CHANNEL 0b00001111
+
+#define FAST 0xA3           // fast PWM both channels
+#define PHASE 0xA1          // phase-correct PWM both channels
+
diff --git a/hwdef-Ferrero_Rocher.h b/hwdef-Ferrero_Rocher.h
new file mode 100644
index 0000000..a46f19d
--- /dev/null
+++ b/hwdef-Ferrero_Rocher.h
@@ -0,0 +1,11 @@
+/* Ferrero Rocher driver layout
+ *            ----
+ *    Reset -|1  8|- VCC
+ * E-switch -|2  7|- Voltage ADC
+ *  Red LED -|3  6|- PWM
+ *      GND -|4  5|- Green LED
+ *            ----
+ */
+// TODO: fill in this section, update Ferrero_Rocher code to use it.
+#define FAST 0x23           // fast PWM channel 1 only
+#define PHASE 0x21          // phase-correct PWM channel 1 only
diff --git a/hwdef-TK_Saber.h b/hwdef-TK_Saber.h
new file mode 100644
index 0000000..e90d5dd
--- /dev/null
+++ b/hwdef-TK_Saber.h
@@ -0,0 +1,33 @@
+/* TK 4-color lightsaber driver layout
+ *             ----
+ *     Reset -|1  8|- VCC
+ * PWM 4 (A) -|2  7|- e-switch
+ * PWM 3 (G) -|3  6|- PWM 2 (B)
+ *       GND -|4  5|- PWM 1 (R)
+ *             ----
+ */
+
+#define PWM_CHANNELS 4
+#define PWM1_PIN PB0        // pin 5
+#define PWM1_LVL OCR0A
+#define PWM2_PIN PB1        // pin 6
+#define PWM2_LVL OCR0B
+#define PWM3_PIN PB4        // pin 3
+#define PWM3_LVL OCR1B
+#define PWM4_PIN PB3        // pin 2
+#define PWM4_LVL OCR1A
+
+#define SWITCH_PIN   PB2    // pin 7
+#define SWITCH_PCINT PCINT2 // pin 7 pin change interrupt
+
+#define ADC_PRSCL   0x06    // clk/64 (no need to be super fast)
+
+// average drop across diode on this hardware
+#define VOLTAGE_FUDGE_FACTOR 5  // add 0.25V
+
+//#define TEMP_DIDR   ADC4D
+#define TEMP_CHANNEL 0b00001111
+
+#define FAST        0xA3    // fast PWM both channels
+#define PHASE       0xA1    // phase-correct PWM both channels
+
diff --git a/hwdef-Tripledown.h b/hwdef-Tripledown.h
new file mode 100644
index 0000000..4676e69
--- /dev/null
+++ b/hwdef-Tripledown.h
@@ -0,0 +1,33 @@
+/* Tripledown driver layout
+ *             ----
+ *     Reset -|1  8|- VCC
+ *       OTC -|2  7|- Voltage ADC
+ * PWM (FET) -|3  6|- PWM (6x7135)
+ *       GND -|4  5|- PWM (1x7135)
+ *             ----
+ */
+
+#define STAR2_PIN   PB0     // If this pin isn't used for ALT_PWM
+
+#define CAP_PIN     PB3     // pin 2, OTC
+#define CAP_CHANNEL 0x03    // MUX 03 corresponds with PB3 (Star 4)
+#define CAP_DIDR    ADC3D   // Digital input disable bit corresponding with PB3
+
+#define PWM_PIN     PB1     // pin 6, 6x7135 PWM
+#define PWM_LVL     OCR0B   // OCR0B is the output compare register for PB1
+#define ALT_PWM_PIN PB0     // pin 5, 1x7135 PWM
+#define ALT_PWM_LVL OCR0A   // OCR0A is the output compare register for PB0
+#define FET_PWM_PIN PB4     // pin 3
+#define FET_PWM_LVL OCR1B   // output compare register for PB4
+
+#define VOLTAGE_PIN PB2     // pin 7, voltage ADC
+#define ADC_CHANNEL 0x01    // MUX 01 corresponds with PB2
+#define ADC_DIDR    ADC1D   // Digital input disable bit corresponding with PB2
+#define ADC_PRSCL   0x06    // clk/64
+
+//#define TEMP_DIDR   ADC4D
+#define TEMP_CHANNEL 0b00001111
+
+#define FAST 0xA3           // fast PWM both channels
+#define PHASE 0xA1          // phase-correct PWM both channels
+
diff --git a/hwdef-nanjg.h b/hwdef-nanjg.h
new file mode 100644
index 0000000..add10d1
--- /dev/null
+++ b/hwdef-nanjg.h
@@ -0,0 +1,16 @@
+/* NANJG driver layout
+ */
+#define STAR2_PIN   PB0
+#define STAR3_PIN   PB4
+#define STAR4_PIN   PB3
+#define PWM_PIN     PB1
+#define VOLTAGE_PIN PB2
+#define ADC_CHANNEL 0x01    // MUX 01 corresponds with PB2
+#define ADC_DIDR    ADC1D   // Digital input disable bit corresponding with PB2
+#define ADC_PRSCL   0x06    // clk/64
+
+#define PWM_LVL     OCR0B   // OCR0B is the output compare register for PB1
+
+#define FAST 0x23           // fast PWM channel 1 only
+#define PHASE 0x21          // phase-correct PWM channel 1 only
+