merged Noctigon KR4 branch, including recent ADC+thermal rewrite

10 files changed, 156 insertions, 9 deletions

diff --git a/hwdef-BLF_GT.h b/hwdef-BLF_GT.h
index 8ad99c7..99adc8f 100644
--- a/hwdef-BLF_GT.h
+++ b/hwdef-BLF_GT.h
@@ -42,7 +42,7 @@
 // 1.1V reference, no left-adjust, ADC1/PB2
 #define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL)
 #endif
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line)
 #ifndef ADC_44
diff --git a/hwdef-Emisar_D18.h b/hwdef-Emisar_D18.h
index 638dadb..3046143 100644
--- a/hwdef-Emisar_D18.h
+++ b/hwdef-Emisar_D18.h
@@ -33,7 +33,7 @@
 #ifndef AUXLED_PIN
 #define AUXLED_PIN PB2      // pin 7
 #endif
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // average drop across diode on this hardware
 #ifndef VOLTAGE_FUDGE_FACTOR
diff --git a/hwdef-Emisar_D4.h b/hwdef-Emisar_D4.h
index be499f1..d3b6802 100644
--- a/hwdef-Emisar_D4.h
+++ b/hwdef-Emisar_D4.h
@@ -34,7 +34,7 @@
 //#define VOLTAGE_PIN PB2     // pin 7, voltage ADC
 //#define ADC_CHANNEL 0x01    // MUX 01 corresponds with PB2
 //#define ADC_DIDR    ADC1D   // Digital input disable bit corresponding with PB2
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // average drop across diode on this hardware
 #ifndef VOLTAGE_FUDGE_FACTOR
diff --git a/hwdef-Emisar_D4Sv2.h b/hwdef-Emisar_D4Sv2.h
index da3a0ca..7c3fe86 100644
--- a/hwdef-Emisar_D4Sv2.h
+++ b/hwdef-Emisar_D4Sv2.h
@@ -52,7 +52,7 @@
 #define PWM3_LVL OCR1B      // OCR1B is the output compare register for PB1
 
 
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // average drop across diode on this hardware
 #ifndef VOLTAGE_FUDGE_FACTOR
diff --git a/hwdef-Emisar_D4v2.h b/hwdef-Emisar_D4v2.h
index addf429..60f3fae 100644
--- a/hwdef-Emisar_D4v2.h
+++ b/hwdef-Emisar_D4v2.h
@@ -48,7 +48,7 @@
 #define PWM2_LVL OCR1B      // OCR1B is the output compare register for PB1
 
 
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // average drop across diode on this hardware
 #ifndef VOLTAGE_FUDGE_FACTOR
diff --git a/hwdef-FW3A.h b/hwdef-FW3A.h
index 0b94635..a223b08 100644
--- a/hwdef-FW3A.h
+++ b/hwdef-FW3A.h
@@ -35,7 +35,7 @@
 //#define ADC_CHANNEL 0x01    // MUX 01 corresponds with PB2
 //#define ADC_DIDR    ADC1D   // Digital input disable bit corresponding with PB2
 #endif
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // average drop across diode on this hardware
 #ifndef VOLTAGE_FUDGE_FACTOR
diff --git a/hwdef-Mateminco_MF01-Mini.h b/hwdef-Mateminco_MF01-Mini.h
index 6c420d7..0fea1e2 100644
--- a/hwdef-Mateminco_MF01-Mini.h
+++ b/hwdef-Mateminco_MF01-Mini.h
@@ -34,7 +34,7 @@
 #define PWM3_LVL OCR1B      // OCR1B is the output compare register for PB4
 #endif
 
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // average drop across diode on this hardware
 #ifndef VOLTAGE_FUDGE_FACTOR
diff --git a/hwdef-Mateminco_MF01S.h b/hwdef-Mateminco_MF01S.h
index 03508ab..cb5a416 100644
--- a/hwdef-Mateminco_MF01S.h
+++ b/hwdef-Mateminco_MF01S.h
@@ -42,7 +42,7 @@
 // 1.1V reference, no left-adjust, ADC1/PB2
 #define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL)
 #endif
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line)
 #ifndef ADC_44
diff --git a/hwdef-Noctigon_KR4.h b/hwdef-Noctigon_KR4.h
new file mode 100644
index 0000000..f624e64
--- /dev/null
+++ b/hwdef-Noctigon_KR4.h
@@ -0,0 +1,147 @@
+#ifndef HWDEF_NOCTIGON_KR4_H
+#define HWDEF_NOCTIGON_KR4_H
+
+/* Noctigon KR4 driver layout (attiny1634)
+ *
+ * Pin / Name / Function
+ *   1    PA6   FET PWM (direct drive) (PWM1B)
+ *   2    PA5   R: red aux LED (PWM0B)
+ *   3    PA4   G: green aux LED
+ *   4    PA3   B: blue aux LED
+ *   5    PA2   (none)
+ *   6    PA1   (none)
+ *   7    PA0   (none)
+ *   8    GND   GND
+ *   9    VCC   VCC
+ *  10    PC5   (none)
+ *  11    PC4   (none)
+ *  12    PC3   RESET
+ *  13    PC2   (none)
+ *  14    PC1   SCK
+ *  15    PC0   (none) PWM0A
+ *  16    PB3   main LED PWM (linear) (PWM1A)
+ *  17    PB2   MISO / e-switch (PCINT10)
+ *  18    PB1   MOSI / battery voltage (ADC6)
+ *  19    PB0   Opamp power
+ *  20    PA7   (none)
+ *      ADC12   thermal sensor
+ *
+ * Main LED power uses one pin to turn the Opamp on/off,
+ * and one pin to control Opamp power level.
+ * Main brightness control uses the power level pin, with 4 kHz 10-bit PWM.
+ * The on/off pin is only used to turn the main LED on and off,
+ * not to change brightness.
+ * Some models also have a direct-drive FET for turbo.
+ */
+
+#ifdef ATTINY
+#undef ATTINY
+#endif
+#define ATTINY 1634
+#include <avr/io.h>
+
+#define PWM_CHANNELS 2
+#define PWM_BITS 10  // 0 to 1023 at 4 kHz, not 0 to 255 at 16 kHz
+#define PWM_TOP 1023
+
+#define SWITCH_PIN   PB2     // pin 17
+#define SWITCH_PCINT PCINT10 // pin 17 pin change interrupt
+#define SWITCH_PCIE  PCIE1   // PCIE1 is for PCINT[11:8]
+#define SWITCH_PCMSK PCMSK1  // PCMSK1 is for PCINT[11:8]
+#define SWITCH_PORT  PINB    // PINA or PINB or PINC
+#define PCINT_vect   PCINT1_vect  // ISR for PCINT[11:8]
+
+// the button tends to short out the voltage divider,
+// so ignore voltage while the button is being held
+//#define NO_LVP_WHILE_BUTTON_PRESSED
+
+
+#define PWM1_PIN PB3        // pin 16, Opamp reference
+#define PWM1_LVL OCR1A      // OCR1A is the output compare register for PB3
+
+#define PWM2_PIN PA6        // pin 1, DD FET PWM
+#define PWM2_LVL OCR1B      // OCR1B is the output compare register for PA6
+
+#define LED_ENABLE_PIN  PB0    // pin 19, Opamp power
+#define LED_ENABLE_PORT PORTB  // control port for PB0
+
+
+#define USE_VOLTAGE_DIVIDER  // use a dedicated pin, not VCC, because VCC input is flattened
+#define VOLTAGE_PIN PB1      // Pin 18 / PB1 / ADC6
+// pin to ADC mappings are in DS table 19-4
+#define VOLTAGE_ADC      ADC6D  // digital input disable pin for PB1
+// DIDR0/DIDR1 mappings are in DS section 19.13.5, 19.13.6
+#define VOLTAGE_ADC_DIDR DIDR1  // DIDR channel for ADC6D
+// DS tables 19-3, 19-4
+// Bit   7     6     5      4     3    2    1    0
+//     REFS1 REFS0 REFEN ADC0EN MUX3 MUX2 MUX1 MUX0
+// MUX[3:0] = 0, 1, 1, 0 for ADC6 / PB1
+// divided by ...
+// REFS[1:0] = 1, 0 for internal 1.1V reference
+// other bits reserved
+#define ADMUX_VOLTAGE_DIVIDER 0b10000110
+#define ADC_PRSCL   0x06    // clk/64
+
+// TODO: calibrate this
+// Raw ADC readings at 4.4V and 2.2V
+// calibrate the voltage readout here
+// estimated / calculated values are:
+//   (voltage - D1) * (R2/(R2+R1) * 256 / 1.1)
+// D1, R1, R2 = 0, 330, 100
+#ifndef ADC_44
+//#define ADC_44 981  // raw value at 4.40V
+#define ADC_44 967  // manually tweaked so 4.16V will blink out 4.2
+#endif
+#ifndef ADC_22
+//#define ADC_22 489  // raw value at 2.20V
+#define ADC_22 482  // manually tweaked so 4.16V will blink out 4.2
+#endif
+
+#define TEMP_CHANNEL 0b00001111
+
+// this light has aux LEDs under the optic
+#define AUXLED_R_PIN    PA5    // pin 2
+#define AUXLED_G_PIN    PA4    // pin 3
+#define AUXLED_B_PIN    PA3    // pin 4
+#define AUXLED_RGB_PORT PORTA  // PORTA or PORTB or PORTC
+#define AUXLED_RGB_DDR  DDRA   // DDRA or DDRB or DDRC
+#define AUXLED_RGB_PUE  PUEA   // PUEA or PUEB or PUEC
+
+// with so many pins, doing this all with #ifdefs gets awkward...
+// ... so just hardcode it in each hwdef file instead
+inline void hwdef_setup() {
+  // enable output ports
+  // Opamp level and Opamp on/off
+  DDRB = (1 << PWM1_PIN)
+       | (1 << LED_ENABLE_PIN);
+  // DD FET PWM, aux R/G/B
+  DDRA = (1 << PWM2_PIN)
+       | (1 << AUXLED_R_PIN)
+       | (1 << AUXLED_G_PIN)
+       | (1 << AUXLED_B_PIN)
+       ;
+
+  // configure PWM
+  // Setup PWM. F_pwm = F_clkio / 2 / N / TOP, where N = prescale factor, TOP = top of counter
+  // pre-scale for timer: N = 1
+  // WGM1[3:0]: 0,0,1,1: PWM, Phase Correct, 10-bit (DS table 12-5)
+  // CS1[2:0]:    0,0,1: clk/1 (No prescaling) (DS table 12-6)
+  // COM1A[1:0]:    1,0: PWM OC1A in the normal direction (DS table 12-4)
+  // COM1B[1:0]:    1,0: PWM OC1B in the normal direction (DS table 12-4)
+  TCCR1A  = (1<<WGM11)  | (1<<WGM10)   // 10-bit (TOP=0x03FF) (DS table 12-5)
+          | (1<<COM1A1) | (0<<COM1A0)  // PWM 1A in normal direction (DS table 12-4)
+          | (1<<COM1B1) | (0<<COM1B0)  // PWM 1B in normal direction (DS table 12-4)
+          ;
+  TCCR1B  = (0<<CS12)   | (0<<CS11) | (1<<CS10)  // clk/1 (no prescaling) (DS table 12-6)
+          | (0<<WGM13)  | (0<<WGM12)  // phase-correct PWM (DS table 12-5)
+          ;
+
+  // set up e-switch
+  //PORTB = (1 << SWITCH_PIN);  // TODO: configure PORTA / PORTB / PORTC?
+  PUEB = (1 << SWITCH_PIN);  // pull-up for e-switch
+  SWITCH_PCMSK = (1 << SWITCH_PCINT);  // enable pin change interrupt
+}
+
+#define LAYOUT_DEFINED
+
+#endif
diff --git a/hwdef-TK_Saber.h b/hwdef-TK_Saber.h
index 3f49d30..9458398 100644
--- a/hwdef-TK_Saber.h
+++ b/hwdef-TK_Saber.h
@@ -23,7 +23,7 @@
 #define SWITCH_PIN   PB2    // pin 7
 #define SWITCH_PCINT PCINT2 // pin 7 pin change interrupt
 
-#define ADC_PRSCL   0x06    // clk/64 (no need to be super fast)
+#define ADC_PRSCL   0x07    // clk/128
 
 // average drop across diode on this hardware
 #define VOLTAGE_FUDGE_FACTOR 5  // add 0.25V