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| author | Selene ToyKeeper | 2020-03-13 18:04:43 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2020-03-13 18:04:43 -0600 |
| commit | 51aae811654a3b73fa10ab449e22a11c858aa2d1 (patch) | |
| tree | 8bec4aa2d09e834918a9d7a3a89e134e62d9cf56 /hwdef-BLF_GT.h | |
| parent | went back to continuous lowpass because it had the best noise reduction (diff) | |
| download | anduril-51aae811654a3b73fa10ab449e22a11c858aa2d1.tar.gz anduril-51aae811654a3b73fa10ab449e22a11c858aa2d1.tar.bz2 anduril-51aae811654a3b73fa10ab449e22a11c858aa2d1.zip | |
went back to slower clk/128 ADC timing
Diffstat (limited to 'hwdef-BLF_GT.h')
| -rw-r--r-- | hwdef-BLF_GT.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hwdef-BLF_GT.h b/hwdef-BLF_GT.h index 01dbdbd..f0ac103 100644 --- a/hwdef-BLF_GT.h +++ b/hwdef-BLF_GT.h @@ -40,7 +40,7 @@ // 1.1V reference, no left-adjust, ADC1/PB2 #define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL) #endif -#define ADC_PRSCL 0x06 // clk/64 +#define ADC_PRSCL 0x07 // clk/128 // Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line) #ifndef ADC_44 |