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authorSelene ToyKeeper2023-10-10 22:32:00 -0600
committerSelene ToyKeeper2023-10-10 22:32:00 -0600
commit55b5ad0665bb362dc266fd1ed79aa62bb17cd94e (patch)
treef793ece13a64ed6cd69b6a4c8c5426ada3094218 /hwdef-FW3A.h
parentconverted sofirn-sp10-pro to new API (diff)
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converted FW3A to new API
(my FW3A dev host is dead though, so the DD FET channel isn't 100% confirmed to work ... will have to solder together a new dev host at some point)
Diffstat (limited to 'hwdef-FW3A.h')
-rw-r--r--hwdef-FW3A.h51
1 files changed, 0 insertions, 51 deletions
diff --git a/hwdef-FW3A.h b/hwdef-FW3A.h
deleted file mode 100644
index f2b5c8d..0000000
--- a/hwdef-FW3A.h
+++ /dev/null
@@ -1,51 +0,0 @@
-// BLF/TLF FW3A driver layout
-// Copyright (C) 2018-2023 Selene ToyKeeper
-// SPDX-License-Identifier: GPL-3.0-or-later
-#pragma once
-
-/*
- * ----
- * Reset -|1 8|- VCC
- * eswitch -|2 7|- optic nerve
- * FET -|3 6|- 7x7135
- * GND -|4 5|- 1x7135
- * ----
- */
-
-#define PWM_CHANNELS 3
-
-#ifndef SWITCH_PIN
-#define SWITCH_PIN PB3 // pin 2
-#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt
-#endif
-
-#ifndef PWM1_PIN
-#define PWM1_PIN PB0 // pin 5, 1x7135 PWM
-#define PWM1_LVL OCR0A // OCR0A is the output compare register for PB0
-#endif
-#ifndef PWM2_PIN
-#define PWM2_PIN PB1 // pin 6, 7x7135 PWM
-#define PWM2_LVL OCR0B // OCR0B is the output compare register for PB1
-#endif
-#ifndef PWM3_PIN
-#define PWM3_PIN PB4 // pin 3, FET PWM
-#define PWM3_LVL OCR1B // OCR1B is the output compare register for PB4
-#endif
-
-#ifndef VISION_PIN
-#define VISION_PIN PB2 // pin 7, optic nerve
-//#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2
-//#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2
-#endif
-#define ADC_PRSCL 0x07 // clk/128
-
-// average drop across diode on this hardware
-#ifndef VOLTAGE_FUDGE_FACTOR
-#define VOLTAGE_FUDGE_FACTOR 5 // add 0.25V
-#endif
-
-#define FAST 0xA3 // fast PWM both channels
-#define PHASE 0xA1 // phase-correct PWM both channels
-
-#define LAYOUT_DEFINED
-