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| author | Selene ToyKeeper | 2023-10-09 10:54:18 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2023-10-09 10:54:18 -0600 |
| commit | 4b6d6be3b26460bb81b41efcae63cac3a578dfb7 (patch) | |
| tree | 63bdef98fd079ded7e700cdc96866a7b75823d8c /hwdef-Mateminco_MF01S.h | |
| parent | smooth steps: fixed a few corner cases (diff) | |
| download | anduril-4b6d6be3b26460bb81b41efcae63cac3a578dfb7.tar.gz anduril-4b6d6be3b26460bb81b41efcae63cac3a578dfb7.tar.bz2 anduril-4b6d6be3b26460bb81b41efcae63cac3a578dfb7.zip | |
converted old MF01S / MT18S build
Diffstat (limited to 'hwdef-Mateminco_MF01S.h')
| -rw-r--r-- | hwdef-Mateminco_MF01S.h | 61 |
1 files changed, 0 insertions, 61 deletions
diff --git a/hwdef-Mateminco_MF01S.h b/hwdef-Mateminco_MF01S.h deleted file mode 100644 index 0ae30a6..0000000 --- a/hwdef-Mateminco_MF01S.h +++ /dev/null @@ -1,61 +0,0 @@ -// MF01S driver layout -// Copyright (C) 2019-2023 Selene ToyKeeper -// SPDX-License-Identifier: GPL-3.0-or-later -#pragma once - -/* - * ---- - * Reset -|1 8|- VCC (unused) - * eswitch -|2 7|- Voltage divider (2S) - * AUX LED -|3 6|- PWM (FET) - * GND -|4 5|- PWM (smaller FET) - * ---- - */ - -#define PWM_CHANNELS 2 - -#ifndef AUXLED_PIN -#define AUXLED_PIN PB4 // pin 3 -#endif - -#ifndef SWITCH_PIN -#define SWITCH_PIN PB3 // pin 2 -#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt -#endif - -#ifndef PWM1_PIN -#define PWM1_PIN PB0 // pin 5, 1x7135 PWM -#define PWM1_LVL OCR0A // OCR0A is the output compare register for PB0 -#endif -#ifndef PWM2_PIN -#define PWM2_PIN PB1 // pin 6, FET PWM -#define PWM2_LVL OCR0B // OCR0B is the output compare register for PB1 -#endif - -#define USE_VOLTAGE_DIVIDER // use a voltage divider on pin 7, not VCC -#ifndef VOLTAGE_PIN -#define VOLTAGE_PIN PB2 // pin 7, voltage ADC -#define VOLTAGE_CHANNEL 0x01 // MUX 01 corresponds with PB2 -#define VOLTAGE_ADC ADC1D // Digital input disable bit corresponding with PB2 -// inherited from tk-attiny.h -//#define VOLTAGE_ADC_DIDR DIDR0 // DIDR for ADC1 -// 1.1V reference, left-adjust, ADC1/PB2 -//#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | (1 << ADLAR) | VOLTAGE_CHANNEL) -// 1.1V reference, no left-adjust, ADC1/PB2 -#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL) -#endif -#define ADC_PRSCL 0x07 // clk/128 - -// Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line) -#ifndef ADC_44 -#define ADC_44 (234*4) -#endif -#ifndef ADC_22 -#define ADC_22 (117*4) -#endif - -#define FAST 0xA3 // fast PWM both channels -#define PHASE 0xA1 // phase-correct PWM both channels - -#define LAYOUT_DEFINED - |