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| author | Selene ToyKeeper | 2022-04-14 21:32:08 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2022-04-14 21:32:08 -0600 |
| commit | 30a503f84b80cef1a46ecbd33bfd4afd16e08e39 (patch) | |
| tree | 760140f35e4377f9eecc0c740f9e78afe6dbf0b1 /hwdef-Noctigon_KR4.h | |
| parent | sp10-pro: hard reset phase while turning off, fixes shutoff bug without a delay (diff) | |
| download | anduril-30a503f84b80cef1a46ecbd33bfd4afd16e08e39.tar.gz anduril-30a503f84b80cef1a46ecbd33bfd4afd16e08e39.tar.bz2 anduril-30a503f84b80cef1a46ecbd33bfd4afd16e08e39.zip | |
applied new phase-hack flags to other builds where relevant
Diffstat (limited to 'hwdef-Noctigon_KR4.h')
| -rw-r--r-- | hwdef-Noctigon_KR4.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hwdef-Noctigon_KR4.h b/hwdef-Noctigon_KR4.h index 75dd4c6..487d3ac 100644 --- a/hwdef-Noctigon_KR4.h +++ b/hwdef-Noctigon_KR4.h @@ -60,6 +60,9 @@ #define PWM1_PIN PB3 // pin 16, Opamp reference #define PWM1_LVL OCR1A // OCR1A is the output compare register for PB3 #define PWM1_CNT TCNT1 // for dynamic PWM, reset phase +#define PWM1_PHASE_RESET_OFF // force reset while shutting off +#define PWM1_PHASE_RESET_ON // force reset while turning on +#define PWM1_PHASE_SYNC // manual sync while changing level #define PWM2_PIN PA6 // pin 1, DD FET PWM #define PWM2_LVL OCR1B // OCR1B is the output compare register for PA6 |