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| author | Selene ToyKeeper | 2018-06-24 20:10:33 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2018-06-24 20:10:33 -0600 |
| commit | 2e76fafd027c027b23964e6f4c2e27f26732db64 (patch) | |
| tree | 66d68a9afbb0341de5614bc78f6f64137b130e3a /hwdef-nanjg.h | |
| parent | Added D4S to the build-all script. (diff) | |
| parent | Refactored driver/hardware definition code to be one file per driver type. (diff) | |
| download | anduril-2e76fafd027c027b23964e6f4c2e27f26732db64.tar.gz anduril-2e76fafd027c027b23964e6f4c2e27f26732db64.tar.bz2 anduril-2e76fafd027c027b23964e6f4c2e27f26732db64.zip | |
merged updates from FSM branch
Diffstat (limited to '')
| -rw-r--r-- | hwdef-nanjg.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/hwdef-nanjg.h b/hwdef-nanjg.h new file mode 100644 index 0000000..add10d1 --- /dev/null +++ b/hwdef-nanjg.h @@ -0,0 +1,16 @@ +/* NANJG driver layout + */ +#define STAR2_PIN PB0 +#define STAR3_PIN PB4 +#define STAR4_PIN PB3 +#define PWM_PIN PB1 +#define VOLTAGE_PIN PB2 +#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2 +#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2 +#define ADC_PRSCL 0x06 // clk/64 + +#define PWM_LVL OCR0B // OCR0B is the output compare register for PB1 + +#define FAST 0x23 // fast PWM channel 1 only +#define PHASE 0x21 // phase-correct PWM channel 1 only + |