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| author | Selene ToyKeeper | 2023-11-02 17:16:25 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2023-11-02 17:16:25 -0600 |
| commit | 7cb4fe0944b839f28dfd96a88a772cd6a8b58019 (patch) | |
| tree | 8d3b203f1650edc28b1f67e1589e3bc870b33fa6 /hwdef-nanjg.h | |
| parent | added LICENSE (GPLv3) (diff) | |
| download | anduril-7cb4fe0944b839f28dfd96a88a772cd6a8b58019.tar.gz anduril-7cb4fe0944b839f28dfd96a88a772cd6a8b58019.tar.bz2 anduril-7cb4fe0944b839f28dfd96a88a772cd6a8b58019.zip | |
reorganized project files (part 1)
(just moved files, didn't change the contents yet,
and nothing will work without updating #includes and build scripts and stuff)
Diffstat (limited to '')
| -rw-r--r-- | hwdef-nanjg.h | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/hwdef-nanjg.h b/hwdef-nanjg.h deleted file mode 100644 index 135edbc..0000000 --- a/hwdef-nanjg.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef HWDEF_NANJG_H -#define HWDEF_NANJG_H - -/* NANJG driver layout - */ -#define STAR2_PIN PB0 -#define STAR3_PIN PB4 -#define STAR4_PIN PB3 -#define PWM_PIN PB1 -#define VOLTAGE_PIN PB2 -#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2 -#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2 -#define ADC_PRSCL 0x06 // clk/64 - -#define PWM_LVL OCR0B // OCR0B is the output compare register for PB1 - -#define FAST 0x23 // fast PWM channel 1 only -#define PHASE 0x21 // phase-correct PWM channel 1 only - -#define LAYOUT_DEFINED - -#endif |