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| author | Gabriel Hart | 2021-05-04 10:27:44 -0500 |
|---|---|---|
| committer | Gabriel Hart | 2021-05-04 10:27:44 -0500 |
| commit | b249c20b96b6c1f50c5a5df4658afa1ca7cfbb4c (patch) | |
| tree | 0b603d2b13b0462b321f35d340348280cee6688a /tk-attiny.h | |
| parent | Merge from main branch (diff) | |
| download | anduril-b249c20b96b6c1f50c5a5df4658afa1ca7cfbb4c.tar.gz anduril-b249c20b96b6c1f50c5a5df4658afa1ca7cfbb4c.tar.bz2 anduril-b249c20b96b6c1f50c5a5df4658afa1ca7cfbb4c.zip | |
Update 1-Series to use 10 MHz clock and Phase Correct PWM. Add PWM documentation. Also clear thermal offset on factory reset instead of setting it to 21*C.
Diffstat (limited to '')
| -rw-r--r-- | tk-attiny.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tk-attiny.h b/tk-attiny.h index ae70afd..110507b 100644 --- a/tk-attiny.h +++ b/tk-attiny.h @@ -73,7 +73,7 @@ //#define VOLTAGE_ADC_DIDR DIDR0 // set this in hwdef #elif (ATTINY == 412) || (ATTINY == 416) || (ATTINY == 417) || (ATTINY == 816) || (ATTINY == 817) || (ATTINY == 1616) || (ATTINY == 1617) || (ATTINY == 3216) || (ATTINY == 3217) #define AVRXMEGA3 - #define F_CPU 5000000UL + #define F_CPU 10000000UL #define BOGOMIPS (F_CPU/4000) #define EEPSIZE 128 #define DELAY_ZERO_TIME 1020 @@ -155,14 +155,14 @@ } typedef enum { - // Actual clock is 20 MHz, but assume that 5 MHz is the top speed and work from there + // Actual clock is 20 MHz, but assume that 10 MHz is the top speed and work from there // TODO: measure PWM speed and power use at 1.25/2.5/5/10 MHz, to determine which speeds are optimal - clock_div_1 = (CLKCTRL_PDIV_4X_gc | CLKCTRL_PEN_bm), // 5 MHz - clock_div_2 = (CLKCTRL_PDIV_8X_gc | CLKCTRL_PEN_bm), // 2.5 MHz - clock_div_4 = (CLKCTRL_PDIV_16X_gc | CLKCTRL_PEN_bm), // 1.25 MHz - clock_div_8 = (CLKCTRL_PDIV_32X_gc | CLKCTRL_PEN_bm), // 625 kHz - clock_div_16 = (CLKCTRL_PDIV_64X_gc | CLKCTRL_PEN_bm), // 312 kHz, max without changing to the 32 kHz ULP - clock_div_32 = (CLKCTRL_PDIV_64X_gc | CLKCTRL_PEN_bm), // 312 kHz + clock_div_1 = (CLKCTRL_PDIV_2X_gc | CLKCTRL_PEN_bm), // 10 MHz + clock_div_2 = (CLKCTRL_PDIV_4X_gc | CLKCTRL_PEN_bm), // 5 MHz + clock_div_4 = (CLKCTRL_PDIV_8X_gc | CLKCTRL_PEN_bm), // 2.5 MHz + clock_div_8 = (CLKCTRL_PDIV_16X_gc | CLKCTRL_PEN_bm), // 1.25 MHz + clock_div_16 = (CLKCTRL_PDIV_32X_gc | CLKCTRL_PEN_bm), // 625 kHz + clock_div_32 = (CLKCTRL_PDIV_64X_gc | CLKCTRL_PEN_bm), // 312 kHz, max without changing to the 32 kHz ULP clock_div_64 = (CLKCTRL_PDIV_64X_gc | CLKCTRL_PEN_bm), // 312 kHz clock_div_128 = (CLKCTRL_PDIV_64X_gc | CLKCTRL_PEN_bm), // 312 kHz clock_div_256 = (CLKCTRL_PDIV_64X_gc | CLKCTRL_PEN_bm) // 312 kHz |