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| author | Selene ToyKeeper | 2015-10-05 18:19:05 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2015-10-05 18:19:05 -0600 |
| commit | dcbda82b4d8ed49e5434e43951333b36cbc4a770 (patch) | |
| tree | 12cae65293ea0e47ebe69b9ffcb69f928a35cbbb /tk-attiny.h | |
| parent | Added volts+tenths and 8-bar battery check styles. (diff) | |
| parent | Replaced how USE_FILE_DELAY works. (diff) | |
| download | anduril-dcbda82b4d8ed49e5434e43951333b36cbc4a770.tar.gz anduril-dcbda82b4d8ed49e5434e43951333b36cbc4a770.tar.bz2 anduril-dcbda82b4d8ed49e5434e43951333b36cbc4a770.zip | |
merged sandbox -- added Tido's BLF-VLD, updated s7 and added volts+tents battcheck to it, battcheck.py and tk-*.h updates...
Diffstat (limited to 'tk-attiny.h')
| -rw-r--r-- | tk-attiny.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tk-attiny.h b/tk-attiny.h index 9415a97..4fee640 100644 --- a/tk-attiny.h +++ b/tk-attiny.h @@ -84,6 +84,19 @@ // TODO: fill in this section, update Ferrero_Rocher code to use it. #endif // FERRERO_ROCHER_LAYOUT +#ifdef NANJG_LAYOUT +#define STAR2_PIN PB0 +#define STAR3_PIN PB4 +#define STAR4_PIN PB3 +#define PWM_PIN PB1 +#define VOLTAGE_PIN PB2 +#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2 +#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2 +#define ADC_PRSCL 0x06 // clk/64 + +#define PWM_LVL OCR0B // OCR0B is the output compare register for PB1 +#endif // NANJG_LAYOUT + #ifndef PWM_LVL Hey, you need to define an I/O pin layout. #endif |