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-rw-r--r--hwdef-BLF_Q8-T1616.h105
-rw-r--r--hwdef-blf-q8-t1616.h138
-rw-r--r--hwdef-wurkkos-ts10.h11
-rw-r--r--spaghetti-monster/anduril/cfg-blf-q8-t1616.h60
4 files changed, 184 insertions, 130 deletions
diff --git a/hwdef-BLF_Q8-T1616.h b/hwdef-BLF_Q8-T1616.h
deleted file mode 100644
index 25734ba..0000000
--- a/hwdef-BLF_Q8-T1616.h
+++ /dev/null
@@ -1,105 +0,0 @@
-// BLF Q8 driver layout using the Attiny1616
-// Copyright (C) 2021-2023 (FIXME)
-// SPDX-License-Identifier: GPL-3.0-or-later
-#pragma once
-
-/*
- * Driver pinout:
- * eSwitch: PA5
- * Aux LED: PB5
- * PWM FET: PB0 (TCA0 WO0)
- * PWM 1x7135: PB1 (TCA0 WO1)
- * Voltage: VCC
-*/
-
-
-#define LAYOUT_DEFINED
-
-#ifdef ATTINY
-#undef ATTINY
-#endif
-#define ATTINY 1616
-#include <avr/io.h>
-
-#define PWM_CHANNELS 2
-
-#ifndef SWITCH_PIN
-#define SWITCH_PIN PIN5_bp
-#define SWITCH_PORT VPORTA.IN
-#define SWITCH_ISC_REG PORTA.PIN2CTRL
-#define SWITCH_VECT PORTA_PORT_vect
-#define SWITCH_INTFLG VPORTA.INTFLAGS
-#endif
-
-
-// 7135 channel
-#ifndef PWM1_PIN
-#define PWM1_PIN PB1 //
-#define PWM1_LVL TCA0.SINGLE.CMP1 // CMP1 is the output compare register for PB1
-#endif
-
-// FET channel
-#ifndef PWM2_PIN
-#define PWM2_PIN PB0 //
-#define PWM2_LVL TCA0.SINGLE.CMP0 // CMP0 is the output compare register for PB0
-#endif
-
-// average drop across diode on this hardware
-#ifndef VOLTAGE_FUDGE_FACTOR
-#define VOLTAGE_FUDGE_FACTOR 7 // add 0.35V
-#endif
-
-
-// lighted button
-#ifndef AUXLED_PIN
-#define AUXLED_PIN PIN5_bp
-#define AUXLED_PORT PORTB
-#endif
-
-
-// with so many pins, doing this all with #ifdefs gets awkward...
-// ... so just hardcode it in each hwdef file instead
-inline void hwdef_setup() {
-
- // set up the system clock to run at 10 MHz instead of the default 3.33 MHz
- _PROTECTED_WRITE( CLKCTRL.MCLKCTRLB, CLKCTRL_PDIV_2X_gc | CLKCTRL_PEN_bm );
-
- //VPORTA.DIR = ...;
- VPORTB.DIR = PIN0_bm | PIN1_bm | PIN5_bm; // Outputs: Aux LED and PWMs
- //VPORTC.DIR = ...;
-
- // enable pullups on the unused pins to reduce power
- PORTA.PIN0CTRL = PORT_PULLUPEN_bm;
- PORTA.PIN1CTRL = PORT_PULLUPEN_bm;
- PORTA.PIN2CTRL = PORT_PULLUPEN_bm;
- PORTA.PIN3CTRL = PORT_PULLUPEN_bm;
- PORTA.PIN4CTRL = PORT_PULLUPEN_bm;
- PORTA.PIN5CTRL = PORT_PULLUPEN_bm | PORT_ISC_BOTHEDGES_gc; // eSwitch
- PORTA.PIN6CTRL = PORT_PULLUPEN_bm;
- PORTA.PIN7CTRL = PORT_PULLUPEN_bm;
-
- //PORTB.PIN0CTRL = PORT_PULLUPEN_bm; // FET channel
- //PORTB.PIN1CTRL = PORT_PULLUPEN_bm; // 7135 channel
- PORTB.PIN2CTRL = PORT_PULLUPEN_bm;
- PORTB.PIN3CTRL = PORT_PULLUPEN_bm;
- PORTB.PIN4CTRL = PORT_PULLUPEN_bm;
- //PORTB.PIN5CTRL = PORT_PULLUPEN_bm; // Aux LED
-
- PORTC.PIN0CTRL = PORT_PULLUPEN_bm;
- PORTC.PIN1CTRL = PORT_PULLUPEN_bm;
- PORTC.PIN2CTRL = PORT_PULLUPEN_bm;
- PORTC.PIN3CTRL = PORT_PULLUPEN_bm;
-
- // set up the PWM
- // https://ww1.microchip.com/downloads/en/DeviceDoc/ATtiny1614-16-17-DataSheet-DS40002204A.pdf
- // PB0 is TCA0:WO0, use TCA_SINGLE_CMP0EN_bm
- // PB1 is TCA0:WO1, use TCA_SINGLE_CMP1EN_bm
- // PB2 is TCA0:WO2, use TCA_SINGLE_CMP2EN_bm
- // For Fast (Single Slope) PWM use TCA_SINGLE_WGMODE_SINGLESLOPE_gc
- // For Phase Correct (Dual Slope) PWM use TCA_SINGLE_WGMODE_DSBOTTOM_gc
- // See the manual for other pins, clocks, configs, portmux, etc
- TCA0.SINGLE.CTRLB = TCA_SINGLE_CMP0EN_bm | TCA_SINGLE_CMP1EN_bm | TCA_SINGLE_WGMODE_DSBOTTOM_gc;
- TCA0.SINGLE.PER = 255;
- TCA0.SINGLE.CTRLA = TCA_SINGLE_CLKSEL_DIV1_gc | TCA_SINGLE_ENABLE_bm;
-}
-
diff --git a/hwdef-blf-q8-t1616.h b/hwdef-blf-q8-t1616.h
new file mode 100644
index 0000000..d9b981f
--- /dev/null
+++ b/hwdef-blf-q8-t1616.h
@@ -0,0 +1,138 @@
+// BLF Q8 driver layout using the Attiny1616
+// Copyright (C) 2021-2023 gchart, Selene ToyKeeper
+// SPDX-License-Identifier: GPL-3.0-or-later
+#pragma once
+
+/*
+ * (based on Wurkkos TS10 driver layout,
+ * which in turn was based on an older version of this BLF-Q8-t1616 driver)
+ * (should probably merge the two files at some point)
+ * Driver pinout:
+ * eSwitch: PA5
+ * Aux LED: PB5
+ * PWM FET: PB0 (TCA0 WO0)
+ * PWM 1x7135: PB1 (TCA0 WO1)
+ * Voltage: VCC
+ */
+
+#define ATTINY 1616
+#include <avr/io.h>
+
+// nearly all t1616-based FET+1 drivers work pretty much the same
+// (this one has single-color aux like the TS10)
+#define HWDEF_C_FILE hwdef-wurkkos-ts10.c
+
+// allow using aux LEDs as extra channel modes
+#include "chan-aux.h"
+
+// channel modes:
+// * 0. FET+7135 stacked
+// * 1. aux LEDs
+#define NUM_CHANNEL_MODES 2
+enum CHANNEL_MODES {
+ CM_MAIN = 0,
+ CM_AUX
+};
+
+#define DEFAULT_CHANNEL_MODE CM_MAIN
+
+// right-most bit first, modes are in fedcba9876543210 order
+#define CHANNEL_MODES_ENABLED 0b00000001
+
+
+#define PWM_CHANNELS 2 // old, remove this
+
+#define PWM_BITS 16 // dynamic 16-bit, but never goes over 255
+#define PWM_GET PWM_GET8
+#define PWM_DATATYPE uint16_t // is used for PWM_TOPS (which goes way over 255)
+#define PWM_DATATYPE2 uint16_t // only needs 32-bit if ramp values go over 255
+#define PWM1_DATATYPE uint8_t // 1x7135 ramp
+#define PWM2_DATATYPE uint8_t // DD FET ramp
+
+// PWM parameters of both channels are tied together because they share a counter
+#define PWM_TOP TCA0.SINGLE.PERBUF // holds the TOP value for for variable-resolution PWM
+#define PWM_TOP_INIT 255 // highest value used in top half of ramp
+// not necessary when double-buffered "BUF" registers are used
+#define PWM_CNT TCA0.SINGLE.CNT // for resetting phase after each TOP adjustment
+
+// 1x7135 channel
+#define CH1_PIN PB1
+#define CH1_PWM TCA0.SINGLE.CMP1BUF // CMP1 is the output compare register for PB1
+
+// DD FET channel
+#define CH2_PIN PB0
+#define CH2_PWM TCA0.SINGLE.CMP0BUF // CMP0 is the output compare register for PB0
+
+// e-switch
+#define SWITCH_PIN PIN5_bp
+#define SWITCH_PORT VPORTA.IN
+#define SWITCH_ISC_REG PORTA.PIN2CTRL
+#define SWITCH_VECT PORTA_PORT_vect
+#define SWITCH_INTFLG VPORTA.INTFLAGS
+
+// average drop across diode on this hardware
+#ifndef VOLTAGE_FUDGE_FACTOR
+#define VOLTAGE_FUDGE_FACTOR 7 // add 0.35V
+#endif
+
+// lighted button
+#define AUXLED_PIN PIN5_bp
+#define AUXLED_PORT PORTB
+
+
+inline void hwdef_setup() {
+
+ // set up the system clock to run at 10 MHz instead of the default 3.33 MHz
+ _PROTECTED_WRITE( CLKCTRL.MCLKCTRLB,
+ CLKCTRL_PDIV_2X_gc | CLKCTRL_PEN_bm );
+
+ //VPORTA.DIR = ...;
+ // Outputs
+ VPORTB.DIR = PIN0_bm // DD FET
+ | PIN1_bm // 7135
+ | PIN5_bm; // Aux LED
+ //VPORTC.DIR = ...;
+
+ // enable pullups on the unused pins to reduce power
+ PORTA.PIN0CTRL = PORT_PULLUPEN_bm;
+ PORTA.PIN1CTRL = PORT_PULLUPEN_bm;
+ PORTA.PIN2CTRL = PORT_PULLUPEN_bm;
+ PORTA.PIN3CTRL = PORT_PULLUPEN_bm;
+ PORTA.PIN4CTRL = PORT_PULLUPEN_bm;
+ PORTA.PIN5CTRL = PORT_PULLUPEN_bm | PORT_ISC_BOTHEDGES_gc; // eSwitch
+ PORTA.PIN6CTRL = PORT_PULLUPEN_bm;
+ PORTA.PIN7CTRL = PORT_PULLUPEN_bm;
+
+ //PORTB.PIN0CTRL = PORT_PULLUPEN_bm; // FET channel
+ //PORTB.PIN1CTRL = PORT_PULLUPEN_bm; // 7135 channel
+ PORTB.PIN2CTRL = PORT_PULLUPEN_bm;
+ PORTB.PIN3CTRL = PORT_PULLUPEN_bm;
+ PORTB.PIN4CTRL = PORT_PULLUPEN_bm;
+ //PORTB.PIN5CTRL = PORT_PULLUPEN_bm; // Aux LED
+
+ PORTC.PIN0CTRL = PORT_PULLUPEN_bm;
+ PORTC.PIN1CTRL = PORT_PULLUPEN_bm;
+ PORTC.PIN2CTRL = PORT_PULLUPEN_bm;
+ PORTC.PIN3CTRL = PORT_PULLUPEN_bm;
+
+ // set up the PWM
+ // https://ww1.microchip.com/downloads/en/DeviceDoc/ATtiny1614-16-17-DataSheet-DS40002204A.pdf
+ // PB0 is TCA0:WO0, use TCA_SINGLE_CMP0EN_bm
+ // PB1 is TCA0:WO1, use TCA_SINGLE_CMP1EN_bm
+ // PB2 is TCA0:WO2, use TCA_SINGLE_CMP2EN_bm
+ // For Fast (Single Slope) PWM use TCA_SINGLE_WGMODE_SINGLESLOPE_gc
+ // For Phase Correct (Dual Slope) PWM use TCA_SINGLE_WGMODE_DSBOTTOM_gc
+ // See the manual for other pins, clocks, configs, portmux, etc
+ TCA0.SINGLE.CTRLB = TCA_SINGLE_CMP0EN_bm
+ | TCA_SINGLE_CMP1EN_bm
+ | TCA_SINGLE_WGMODE_DSBOTTOM_gc;
+ TCA0.SINGLE.CTRLA = TCA_SINGLE_CLKSEL_DIV1_gc
+ | TCA_SINGLE_ENABLE_bm;
+
+ PWM_TOP = PWM_TOP_INIT;
+
+}
+
+
+#define LAYOUT_DEFINED
+
diff --git a/hwdef-wurkkos-ts10.h b/hwdef-wurkkos-ts10.h
index 4af6a84..e693c99 100644
--- a/hwdef-wurkkos-ts10.h
+++ b/hwdef-wurkkos-ts10.h
@@ -1,5 +1,5 @@
// Wurkkos TS10 driver layout
-// Copyright (C) 2022-2023 (FIXME)
+// Copyright (C) 2021-2023 gchart, Selene ToyKeeper
// SPDX-License-Identifier: GPL-3.0-or-later
#pragma once
@@ -32,6 +32,7 @@ enum CHANNEL_MODES {
#define DEFAULT_CHANNEL_MODE CM_MAIN
+// right-most bit first, modes are in fedcba9876543210 order
#define CHANNEL_MODES_ENABLED 0b00000001
@@ -84,10 +85,10 @@ inline void hwdef_setup() {
CLKCTRL_PDIV_2X_gc | CLKCTRL_PEN_bm );
//VPORTA.DIR = ...;
- // Outputs: Aux LED and PWMs
- VPORTB.DIR = PIN0_bm
- | PIN1_bm
- | PIN5_bm;
+ // Outputs
+ VPORTB.DIR = PIN0_bm // DD FET
+ | PIN1_bm // 7135
+ | PIN5_bm; // Aux LED
//VPORTC.DIR = ...;
// enable pullups on the unused pins to reduce power
diff --git a/spaghetti-monster/anduril/cfg-blf-q8-t1616.h b/spaghetti-monster/anduril/cfg-blf-q8-t1616.h
index a88ab24..9f0402c 100644
--- a/spaghetti-monster/anduril/cfg-blf-q8-t1616.h
+++ b/spaghetti-monster/anduril/cfg-blf-q8-t1616.h
@@ -1,10 +1,11 @@
// BLF Q8 config options for Anduril using the Attiny1616
-// Copyright (C) 2021-2023 (FIXME)
+// Copyright (C) 2021-2023 gchart, Selene ToyKeeper
// SPDX-License-Identifier: GPL-3.0-or-later
#pragma once
#define MODEL_NUMBER "0613"
-#include "hwdef-BLF_Q8-T1616.h"
+#include "hwdef-blf-q8-t1616.h"
+#include "wurkkos-cfg.h" // Sofirn lights are closely related to Wurkkos
// ATTINY: 1616
// the button lights up
@@ -15,28 +16,35 @@
// lockout: blinking (3)
#define INDICATOR_LED_DEFAULT_MODE ((3<<2) + 1)
-// copied from Emisar D4 ramp
-// ../../bin/level_calc.py 1 65 7135 1 0.8 150
-// ... mixed with this:
-// ../../bin/level_calc.py 2 150 7135 4 0.33 150 FET 1 10 1500
-#define RAMP_LENGTH 150
-#define PWM1_LEVELS 1,1,2,2,3,3,4,4,5,6,7,8,9,10,12,13,14,15,17,19,20,22,24,26,29,31,34,36,39,42,45,48,51,55,59,62,66,70,75,79,84,89,93,99,104,110,115,121,127,134,140,147,154,161,168,176,184,192,200,209,217,226,236,245,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0
-#define PWM2_LEVELS 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,3,4,5,7,8,9,11,12,14,15,17,19,20,22,24,25,27,29,31,33,35,37,39,41,43,45,48,50,52,55,57,59,62,64,67,70,72,75,78,81,84,87,90,93,96,99,102,105,109,112,115,119,122,126,129,133,137,141,144,148,152,156,160,165,169,173,177,182,186,191,195,200,205,209,214,219,224,229,234,239,244,250,255
-#define MAX_1x7135 65
-#define HALFSPEED_LEVEL 14
+// copied from Wurkkos TS25 ramp
+#define RAMP_SIZE 150
+// 7135 at 75/150
+// level_calc.py 5.7895 2 150 7135 1 0.1 130 FET 1 10 3000 --pwm dyn:74:4096:255:3
+// (with some manual tweaks)
+#define PWM1_LEVELS 1,1,2,3,3,4,5,6,7,8,9,11,12,13,15,16,18,19,21,23,26,27,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,71,74,76,78,80,82,85,87,90,93,96,100,103,107,112,116,122,127,133,140,147,154,163,171,182,192,203,215,228,241,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0
+// non-zero part of FET channel calculated with:
+// level_calc.py 3 1 75 7135 1 200 3000
+// (FIXME? there's a visible bump when the FET kicks in, even with just 1/255)
+#define PWM2_LEVELS 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,2,3,4,6,7,8,10,11,13,14,16,17,19,21,22,24,26,28,30,32,34,37,39,41,44,46,48,51,54,56,59,62,65,68,71,74,77,81,84,87,91,94,98,102,106,110,114,118,122,126,130,135,139,144,148,153,158,163,168,173,178,184,189,195,200,206,212,218,224,230,236,242,248,255
+#define PWM_TOPS 4095,2701,3200,3586,2518,2778,2834,2795,2705,2587,2455,2582,2412,2247,2256,2091,2062,1907,1860,1802,1737,1605,1542,1477,1412,1347,1284,1222,1162,1105,1050,997,946,898,853,810,768,730,693,658,625,594,564,536,503,485,462,439,418,398,384,366,353,340,327,319,307,298,292,284,280,273,269,266,263,260,258,256,256,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255
+
+#define MAX_1x7135 75
+#define DEFAULT_LEVEL 50
+#define MIN_THERM_STEPDOWN 60
+#define HALFSPEED_LEVEL 20
#define QUARTERSPEED_LEVEL 5
-#define RAMP_SMOOTH_FLOOR 1
-#define RAMP_SMOOTH_CEIL 120
-// 10 28 46 [65] 83 101 120
-#define RAMP_DISCRETE_FLOOR 10
-#define RAMP_DISCRETE_CEIL RAMP_SMOOTH_CEIL
-#define RAMP_DISCRETE_STEPS 7
+#define RAMP_SMOOTH_FLOOR 1
+#define RAMP_SMOOTH_CEIL 150
+// 20 38 56 [75] 93 111 130
+#define RAMP_DISCRETE_FLOOR 20
+#define RAMP_DISCRETE_CEIL 130
+#define RAMP_DISCRETE_STEPS 7
// at Sofirn's request, use max (150) for the Simple UI ceiling
-#define SIMPLE_UI_FLOOR RAMP_DISCRETE_FLOOR
-#define SIMPLE_UI_CEIL 150
-#define SIMPLE_UI_STEPS 5
+#define SIMPLE_UI_FLOOR 1
+#define SIMPLE_UI_CEIL 150
+#define SIMPLE_UI_STEPS 5
// also at Sofirn's request, enable 2 click turbo (Anduril 1 style)
#define DEFAULT_2C_STYLE 1
@@ -54,9 +62,21 @@
// stop panicking at ~75% power or ~3000 lm, this light has high thermal mass
#define THERM_FASTER_LEVEL (RAMP_SIZE*9/10) // throttle back faster when high
+// show each channel while it scroll by in the menu
+#define USE_CONFIG_COLORS
+
+// blink numbers on the aux LEDs by default
+#define DEFAULT_BLINK_CHANNEL CM_AUX
+
+// the default of 26 looks a bit rough, so increase it to make it smoother
+#define CANDLE_AMPLITUDE 33
+
// don't blink during the ramp; the button LED brightness is sufficient
// to indicate which power channel(s) are being used
#ifdef BLINK_AT_RAMP_MIDDLE
#undef BLINK_AT_RAMP_MIDDLE
#endif
+// enable factory reset on 13H without loosening tailcap (required)
+#define USE_SOFT_FACTORY_RESET
+
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-28 22:19:47 +0000