diff options
Diffstat (limited to '')
| -rw-r--r-- | hwdef-noctigon-dm11-boost.c | 63 | ||||
| -rw-r--r-- | hwdef-noctigon-dm11-boost.h | 60 | ||||
| -rw-r--r-- | hwdef-noctigon-m44.h | 22 | ||||
| -rw-r--r-- | spaghetti-monster/anduril/cfg-noctigon-dm11-boost.h | 17 | ||||
| -rw-r--r-- | spaghetti-monster/anduril/smooth-steps.c | 4 | ||||
| -rw-r--r-- | spaghetti-monster/fsm-events.c | 8 | ||||
| -rw-r--r-- | spaghetti-monster/fsm-events.h | 5 |
7 files changed, 126 insertions, 53 deletions
diff --git a/hwdef-noctigon-dm11-boost.c b/hwdef-noctigon-dm11-boost.c index 08e2798..932323a 100644 --- a/hwdef-noctigon-dm11-boost.c +++ b/hwdef-noctigon-dm11-boost.c @@ -1,11 +1,11 @@ // Noctigon DM11 (boost driver) PWM helper functions // Copyright (C) 2023 Selene ToyKeeper // SPDX-License-Identifier: GPL-3.0-or-later - #pragma once #include "chan-rgbaux.c" + void set_level_zero(); void set_level_main(uint8_t level); @@ -22,6 +22,12 @@ Channel channels[] = { void set_level_zero() { + // disable timer overflow interrupt + // (helps improve button press handling from Off state) + DSM_INTCTRL &= ~DSM_OVF_bm; + + // turn off all LEDs + ch1_dsm_lvl = 0; CH1_PWM = 0; PWM_CNT = 0; // reset phase CH1_ENABLE_PORT &= ~(1 << CH1_ENABLE_PIN ); // disable opamp @@ -30,28 +36,59 @@ void set_level_zero() { // single set of LEDs with single power channel, boost void set_level_main(uint8_t level) { - CH1_ENABLE_PORT |= (1 << CH1_ENABLE_PIN ); // enable opamp - CH1_ENABLE_PORT2 |= (1 << CH1_ENABLE_PIN2); // enable PMIC + PWM_DATATYPE ch1 = PWM_GET(pwm1_levels, level); - PWM_DATATYPE ch1_pwm = PWM_GET(pwm1_levels, level); - // pulse frequency modulation, a.k.a. dynamic PWM - uint16_t top = PWM_GET16(pwm_tops, level); + // set delta-sigma soft levels + ch1_dsm_lvl = ch1; + + // set hardware PWM levels and init dsm loop + CH1_PWM = ch1_pwm = ch1 >> 7; + + // enable timer overflow interrupt so DSM can work + DSM_INTCTRL |= DSM_OVF_bm; - CH1_PWM = ch1_pwm; - // wait to sync the counter and avoid flashes - while(actual_level && (PWM_CNT > (top - 32))) {} - PWM_TOP = top; // force reset phase when turning on from zero // (because otherwise the initial response is inconsistent) if (! actual_level) PWM_CNT = 0; + + CH1_ENABLE_PORT |= (1 << CH1_ENABLE_PIN ); // enable opamp + CH1_ENABLE_PORT2 |= (1 << CH1_ENABLE_PIN2); // enable PMIC } +// delta-sigma modulation of PWM outputs +// happens on each Timer overflow (every 512 cpu clock cycles) +// uses 8-bit pwm w/ 7-bit dsm (0b 0PPP PPPP PDDD DDDD) +ISR(DSM_vect) { + // set new hardware values first, + // for best timing (reduce effect of interrupt jitter) + CH1_PWM = ch1_pwm; + + // calculate next values, now that timing matters less + + // accumulate error + ch1_dsm += (ch1_dsm_lvl & 0x007f); + // next PWM = base PWM value + carry bit + ch1_pwm = (ch1_dsm_lvl >> 7) + (ch1_dsm > 0x7f); + // clear carry bit + ch1_dsm &= 0x7f; +} + + bool gradual_tick_main(uint8_t gt) { - PWM_DATATYPE pwm1 = PWM_GET(pwm1_levels, gt); + PWM_DATATYPE ch1 = PWM_GET(pwm1_levels, gt); + + // adjust multiple times based on current brightness + // (so it adjusts faster/coarser when bright, slower/finer when dim) + + // higher shift = slower/finer adjustments + const uint8_t shift = 9; // ((255 << 7) >> 9) = 63 max + uint8_t steps; - GRADUAL_ADJUST_SIMPLE(pwm1, CH1_PWM); + steps = ch1_dsm_lvl >> shift; + for (uint8_t i=0; i<=steps; i++) + GRADUAL_ADJUST_SIMPLE(ch1, ch1_dsm_lvl); - if ( (pwm1 == CH1_PWM) + if ((ch1 == ch1_dsm_lvl) ) { return true; // done } diff --git a/hwdef-noctigon-dm11-boost.h b/hwdef-noctigon-dm11-boost.h index 4453bc7..d56a5f5 100644 --- a/hwdef-noctigon-dm11-boost.h +++ b/hwdef-noctigon-dm11-boost.h @@ -31,7 +31,7 @@ * * Main LED power uses one pin to turn the Opamp on/off, * and one pin to control Opamp power level. - * Linear brightness control uses the power level pin, with dynamic PWM. + * Regulated brightness control uses the power level pin, with PWM+DSM. * The on/off pin is only used to turn the main LED on and off, * not to change brightness. */ @@ -62,35 +62,46 @@ enum CHANNEL_MODES { //#define CHANNEL_MODE_ARGS 0,0,0,0,0,0,0,0 -#define PWM_CHANNELS 1 // old, remove this +#define PWM_CHANNELS 1 // old, remove this -#define PWM_BITS 16 // dynamic 16-bit, but never goes over 255 -#define PWM_GET PWM_GET8 -#define PWM_DATATYPE uint16_t // is used for PWM_TOPS (which goes way over 255) -#define PWM_DATATYPE2 uint16_t // only needs 32-bit if ramp values go over 255 -#define PWM1_DATATYPE uint8_t // regulated ramp +#define PWM_BITS 16 // 0 to 32640 (0 to 255 PWM + 0 to 127 DSM) at constant kHz +#define PWM_GET PWM_GET16 +#define PWM_DATATYPE uint16_t +#define PWM_DATATYPE2 uint32_t // only needs 32-bit if ramp values go over 255 +#define PWM1_DATATYPE uint16_t // 15-bit PWM+DSM ramp #define PWM_TOP ICR1 // holds the TOP value for variable-resolution PWM -#define PWM_TOP_INIT 255 // highest value used in top half of ramp -#define PWM_CNT TCNT1 // for dynamic PWM, reset phase +#define PWM_TOP_INIT 255 +#define PWM_CNT TCNT1 // for checking / resetting phase +// (max is (255 << 7), because it's 8-bit PWM plus 7 bits of DSM) +#define DSM_TOP (255<<7) // 15-bit resolution leaves 1 bit for carry + +// timer interrupt for DSM +#define DSM_vect TIMER1_OVF_vect +#define DSM_INTCTRL TIMSK +#define DSM_OVF_bm (1<<TOIE1) + +#define DELAY_FACTOR 90 // less time in delay() because more time spent in interrupts // regulated channel -#define CH1_PIN PB3 // pin 16, Opamp reference -#define CH1_PWM OCR1A // OCR1A is the output compare register for PB3 +uint16_t ch1_dsm_lvl; +uint8_t ch1_pwm, ch1_dsm; +#define CH1_PIN PB3 // pin 16, Opamp reference +#define CH1_PWM OCR1A // OCR1A is the output compare register for PB3 -#define CH1_ENABLE_PIN PB0 // pin 19, Opamp power -#define CH1_ENABLE_PORT PORTB // control port for PB0 +#define CH1_ENABLE_PIN PB0 // pin 19, Opamp power +#define CH1_ENABLE_PORT PORTB // control port for PB0 #define CH1_ENABLE_PIN2 PC0 // pin 15, boost PMIC enable #define CH1_ENABLE_PORT2 PORTC // control port for PC0 // e-switch -#define SWITCH_PIN PA7 // pin 20 -#define SWITCH_PCINT PCINT7 // pin 20 pin change interrupt -#define SWITCH_PCIE PCIE0 // PCIE0 is for PCINT[7:0] -#define SWITCH_PCMSK PCMSK0 // PCMSK0 is for PCINT[7:0] -#define SWITCH_PORT PINA // PINA or PINB or PINC -#define SWITCH_PUE PUEA // pullup group A +#define SWITCH_PIN PA7 // pin 20 +#define SWITCH_PCINT PCINT7 // pin 20 pin change interrupt +#define SWITCH_PCIE PCIE0 // PCIE0 is for PCINT[7:0] +#define SWITCH_PCMSK PCMSK0 // PCMSK0 is for PCINT[7:0] +#define SWITCH_PORT PINA // PINA or PINB or PINC +#define SWITCH_PUE PUEA // pullup group A #define PCINT_vect PCINT0_vect // ISR for PCINT[7:0] #define USE_VOLTAGE_DIVIDER // use a dedicated pin, not VCC, because VCC input is flattened @@ -163,21 +174,28 @@ inline void hwdef_setup() { // configure PWM // Setup PWM. F_pwm = F_clkio / 2 / N / TOP, where N = prescale factor, TOP = top of counter // pre-scale for timer: N = 1 + // PWM for both channels // WGM1[3:0]: 1,0,1,0: PWM, Phase Correct, adjustable (DS table 12-5) + // WGM1[3:0]: 1,1,1,0: PWM, Fast, adjustable (DS table 12-5) // CS1[2:0]: 0,0,1: clk/1 (No prescaling) (DS table 12-6) // COM1A[1:0]: 1,0: PWM OC1A in the normal direction (DS table 12-4) - // COM1B[1:0]: 0,0: PWM OC1B disabled (DS table 12-4) + // COM1B[1:0]: 1,0: PWM OC1B in the normal direction (DS table 12-4) TCCR1A = (1<<WGM11) | (0<<WGM10) // adjustable PWM (TOP=ICR1) (DS table 12-5) | (1<<COM1A1) | (0<<COM1A0) // PWM 1A in normal direction (DS table 12-4) - | (0<<COM1B1) | (0<<COM1B0) // PWM 1B disabled (DS table 12-4) + | (1<<COM1B1) | (0<<COM1B0) // PWM 1B in normal direction (DS table 12-4) ; TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6) + //| (1<<WGM13) | (1<<WGM12) // fast adjustable PWM (DS table 12-5) | (1<<WGM13) | (0<<WGM12) // phase-correct adjustable PWM (DS table 12-5) ; // set PWM resolution PWM_TOP = PWM_TOP_INIT; + // set up interrupt for delta-sigma modulation + // (moved to hwdef.c functions so it can be enabled/disabled based on ramp level) + //DSM_INTCTRL |= DSM_OVF_bm; // interrupt once for each timer cycle + // set up e-switch SWITCH_PUE = (1 << SWITCH_PIN); // pull-up for e-switch SWITCH_PCMSK = (1 << SWITCH_PCINT); // enable pin change interrupt diff --git a/hwdef-noctigon-m44.h b/hwdef-noctigon-m44.h index a41ea79..094e555 100644 --- a/hwdef-noctigon-m44.h +++ b/hwdef-noctigon-m44.h @@ -65,7 +65,7 @@ enum channel_modes_e { #define PWM_CHANNELS 1 // old, remove this -#define PWM_BITS 16 // 0 to 32640 (0 to 255 PWM + 0 to 127 DSM) at constant kHz +#define PWM_BITS 16 // 0 to 32640 (0 to 255 PWM + 0 to 127 DSM) at constant kHz #define PWM_GET PWM_GET16 #define PWM_DATATYPE uint16_t #define PWM_DATATYPE2 uint32_t // only needs 32-bit if ramp values go over 255 @@ -105,8 +105,8 @@ uint8_t ch2_pwm, ch2_dsm; // e-switch #define SWITCH_PIN PA7 // pin 20 #define SWITCH_PCINT PCINT7 // pin 20 pin change interrupt -#define SWITCH_PCIE PCIE0 // PCIE1 is for PCINT[7:0] -#define SWITCH_PCMSK PCMSK0 // PCMSK1 is for PCINT[7:0] +#define SWITCH_PCIE PCIE0 // PCIE0 is for PCINT[7:0] +#define SWITCH_PCMSK PCMSK0 // PCMSK0 is for PCINT[7:0] #define SWITCH_PORT PINA // PINA or PINB or PINC #define SWITCH_PUE PUEA // pullup group A #define PCINT_vect PCINT0_vect // ISR for PCINT[7:0] @@ -178,14 +178,14 @@ inline void hwdef_setup() { // CS1[2:0]: 0,0,1: clk/1 (No prescaling) (DS table 12-6) // COM1A[1:0]: 1,0: PWM OC1A in the normal direction (DS table 12-4) // COM1B[1:0]: 1,0: PWM OC1B in the normal direction (DS table 12-4) - TCCR1A = (1<<WGM11) | (0<<WGM10) // adjustable PWM (TOP=ICR1) (DS table 12-5) - | (1<<COM1A1) | (0<<COM1A0) // PWM 1A in normal direction (DS table 12-4) - | (1<<COM1B1) | (0<<COM1B0) // PWM 1B in normal direction (DS table 12-4) - ; - TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6) - //| (1<<WGM13) | (1<<WGM12) // fast adjustable PWM (DS table 12-5) - | (1<<WGM13) | (0<<WGM12) // phase-correct adjustable PWM (DS table 12-5) - ; + TCCR1A = (1<<WGM11) | (0<<WGM10) // adjustable PWM (TOP=ICR1) (DS table 12-5) + | (1<<COM1A1) | (0<<COM1A0) // PWM 1A in normal direction (DS table 12-4) + | (1<<COM1B1) | (0<<COM1B0) // PWM 1B in normal direction (DS table 12-4) + ; + TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6) + //| (1<<WGM13) | (1<<WGM12) // fast adjustable PWM (DS table 12-5) + | (1<<WGM13) | (0<<WGM12) // phase-correct adjustable PWM (DS table 12-5) + ; // set PWM resolution PWM_TOP = PWM_TOP_INIT; diff --git a/spaghetti-monster/anduril/cfg-noctigon-dm11-boost.h b/spaghetti-monster/anduril/cfg-noctigon-dm11-boost.h index 5c5db00..2174fdb 100644 --- a/spaghetti-monster/anduril/cfg-noctigon-dm11-boost.h +++ b/spaghetti-monster/anduril/cfg-noctigon-dm11-boost.h @@ -14,18 +14,31 @@ // - boost: 8A? // - DD FET: none (can't do DD on a boost driver) +#if 0 // old, dynamic PWM method // level_calc.py 5.01 1 149 7135 1 0.3 1740 --pwm dyn:78:16384:255 // (plus a 0 at the beginning for moon) #define PWM1_LEVELS 0,1,1,1,2,3,3,4,5,6,7,8,9,10,11,13,14,16,17,19,21,23,25,27,29,31,34,36,39,42,44,47,50,53,57,60,63,67,70,74,77,81,85,88,92,96,99,103,107,110,113,117,120,123,126,128,130,133,134,136,137,137,137,137,136,135,133,130,126,122,117,111,104,96,87,76,65,52,38,22,23,25,26,27,28,29,30,32,33,34,36,37,39,40,42,43,45,47,49,51,53,55,57,59,61,63,66,68,70,73,76,78,81,84,87,90,93,96,99,103,106,110,113,117,121,125,129,133,137,142,146,151,155,160,165,170,175,181,186,192,197,203,209,215,222,228,234,241,248,255 #define PWM_TOPS 16383,16383,12404,8140,11462,14700,11041,12947,13795,14111,14124,13946,13641,13248,12791,13418,12808,13057,12385,12428,12358,12209,12000,11746,11459,11147,11158,10793,10708,10576,10173,9998,9800,9585,9527,9278,9023,8901,8634,8486,8216,8053,7881,7615,7440,7261,7009,6832,6656,6422,6196,6031,5819,5615,5419,5190,4973,4803,4571,4386,4179,3955,3745,3549,3340,3145,2940,2729,2513,2312,2109,1903,1697,1491,1286,1070,871,662,459,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255 - #define MAX_1x7135 150 #define DEFAULT_LEVEL 70 #define MIN_THERM_STEPDOWN 80 // must be > end of dynamic PWM range #define HALFSPEED_LEVEL 12 #define QUARTERSPEED_LEVEL 4 +#endif + +// delta-sigma modulated PWM (0b0HHHHHHHHLLLLLLL = 0, 8xHigh, 7xLow bits) +// level_calc.py 5.01 1 150 7135 0 0.2 2000 --pwm 32640 +// (max is (255 << 7), because it's 8-bit PWM plus 7 bits of DSM) +#define PWM1_LEVELS 0,1,2,3,4,5,6,7,9,10,12,14,17,19,22,25,28,32,36,41,45,50,56,62,69,76,84,92,101,110,121,132,143,156,169,184,199,215,232,251,270,291,313,336,360,386,414,442,473,505,539,574,612,651,693,736,782,829,880,932,987,1045,1105,1168,1233,1302,1374,1449,1527,1608,1693,1781,1873,1969,2068,2172,2279,2391,2507,2628,2753,2883,3018,3158,3303,3454,3609,3771,3938,4111,4289,4475,4666,4864,5068,5280,5498,5724,5957,6197,6445,6701,6965,7237,7518,7808,8106,8413,8730,9056,9392,9737,10093,10459,10835,11223,11621,12031,12452,12884,13329,13786,14255,14737,15232,15741,16262,16798,17347,17911,18489,19082,19691,20314,20954,21609,22281,22969,23674,24397,25137,25895,26671,27465,28279,29111,29963,30835,31727,32640 +#define MIN_THERM_STEPDOWN 50 +#define DEFAULT_LEVEL 70 +#define MAX_1x7135 150 +// always run at 1/4th speed, because 4 kHz PWM is enough for this circuit +// and speed changes make a big visible bump +#define HALFSPEED_LEVEL 255 +#define QUARTERSPEED_LEVEL 255 -#define RAMP_SMOOTH_FLOOR 10 // low levels may be unreliable +#define RAMP_SMOOTH_FLOOR 1 // low levels may be unreliable #define RAMP_SMOOTH_CEIL 130 // 10, 30, 50, [70], 90, 110, 130 // Nichia B35 model: (0.56), 1.4, 8.4, 34.5, [102], 250, 500, 860, (1300) lm diff --git a/spaghetti-monster/anduril/smooth-steps.c b/spaghetti-monster/anduril/smooth-steps.c index d907bc1..b8664bd 100644 --- a/spaghetti-monster/anduril/smooth-steps.c +++ b/spaghetti-monster/anduril/smooth-steps.c @@ -23,12 +23,12 @@ void smooth_steps_iter() { uint8_t this = diff / smooth_steps_speed; if (!this) this = 1; set_level(actual_level + this); - nice_delay_ms(10); + nice_delay_ms(9); } else { // ramp-linear descent // (jump by 1 on each frame, frame rate gives constant total time) uint8_t diff = smooth_steps_start - smooth_steps_target; - uint16_t delay = 1 + (26 * smooth_steps_speed / diff); + uint16_t delay = 1 + (22 * smooth_steps_speed / diff); set_level(actual_level - 1); // TODO? if delay < one PWM cycle, this can look a little weird nice_delay_ms(delay); diff --git a/spaghetti-monster/fsm-events.c b/spaghetti-monster/fsm-events.c index ffa93d1..6987ae2 100644 --- a/spaghetti-monster/fsm-events.c +++ b/spaghetti-monster/fsm-events.c @@ -127,7 +127,7 @@ uint8_t nice_delay_ms(uint16_t ms) { uint8_t level = actual_level; // volatile, avoid repeat access if (level < QUARTERSPEED_LEVEL) { clock_prescale_set(clock_div_4); - _delay_loop_2(BOGOMIPS*90/100/4); + _delay_loop_2(BOGOMIPS*DELAY_FACTOR/100/4); } //else if (level < HALFSPEED_LEVEL) { // clock_prescale_set(clock_div_2); @@ -135,7 +135,7 @@ uint8_t nice_delay_ms(uint16_t ms) { //} else { clock_prescale_set(clock_div_1); - _delay_loop_2(BOGOMIPS*90/100); + _delay_loop_2(BOGOMIPS*DELAY_FACTOR/100); } // restore regular clock speed clock_prescale_set(clock_div_1); @@ -143,13 +143,13 @@ uint8_t nice_delay_ms(uint16_t ms) { // underclock MCU to save power clock_prescale_set(clock_div_4); // wait - _delay_loop_2(BOGOMIPS*90/100/4); + _delay_loop_2(BOGOMIPS*DELAY_FACTOR/100/4); // restore regular clock speed clock_prescale_set(clock_div_1); #endif // ifdef USE_RAMPING #else // wait - _delay_loop_2(BOGOMIPS*90/100); + _delay_loop_2(BOGOMIPS*DELAY_FACTOR/100); #endif // ifdef USE_DYNAMIC_UNDERCLOCKING // run pending system processes while we wait diff --git a/spaghetti-monster/fsm-events.h b/spaghetti-monster/fsm-events.h index 10d3317..9692163 100644 --- a/spaghetti-monster/fsm-events.h +++ b/spaghetti-monster/fsm-events.h @@ -54,6 +54,11 @@ uint8_t push_event(uint8_t ev_type); // only for use by PCINT_inner() // TODO: Maybe move these to their own file... // ... this probably isn't the right place for delays. +#ifndef DELAY_FACTOR +// adjust the timing of delays, lower = shorter delays +// 90 = 90% delay, 10% for other things +#define DELAY_FACTOR 92 +#endif inline void interrupt_nice_delays(); uint8_t nice_delay_ms(uint16_t ms); //uint8_t nice_delay_s(); |