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-rw-r--r--hwdef-fw3x-lume1.c60
-rw-r--r--hwdef-fw3x-lume1.h170
-rw-r--r--hwdef-noctigon-kr4.c1
-rw-r--r--hwdef-noctigon-kr4.h2
-rw-r--r--spaghetti-monster/anduril/cfg-fw3x-lume1.h22
5 files changed, 168 insertions, 87 deletions
diff --git a/hwdef-fw3x-lume1.c b/hwdef-fw3x-lume1.c
new file mode 100644
index 0000000..2f31ed0
--- /dev/null
+++ b/hwdef-fw3x-lume1.c
@@ -0,0 +1,60 @@
+// FW3X Lume1 PWM helper functions
+// Copyright (C) 2023 Selene ToyKeeper
+// SPDX-License-Identifier: GPL-3.0-or-later
+#pragma once
+
+#include "chan-rgbaux.c"
+
+void set_level_zero();
+
+void set_level_main(uint8_t level);
+bool gradual_tick_main(uint8_t gt);
+
+
+Channel channels[] = {
+ { // channel 1 only
+ .set_level = set_level_main,
+ .gradual_tick = gradual_tick_main
+ },
+ RGB_AUX_CHANNELS
+};
+
+
+void set_level_zero() {
+ CH1_PWM = 0;
+ CH2_PWM = 0;
+ PWM_CNT = 0; // reset phase
+ CH1_ENABLE_PORT &= ~(1 << CH1_ENABLE_PIN); // disable regulator
+}
+
+// single set of LEDs with 2 stacked power channels, regulated + DD FET
+void set_level_main(uint8_t level) {
+ CH1_ENABLE_PORT |= (1 << CH1_ENABLE_PIN); // enable regulator
+
+ PWM_DATATYPE ch1_pwm = PWM_GET(pwm1_levels, level);
+ PWM_DATATYPE ch2_pwm = PWM_GET(pwm2_levels, level);
+
+ CH1_PWM = ch1_pwm;
+ CH2_PWM = ch2_pwm;
+
+ // force reset phase when turning on from zero
+ // (for faster, more consistent initial response)
+ if (! actual_level) PWM_CNT = 0;
+}
+
+bool gradual_tick_main(uint8_t gt) {
+ // 150/150 is full FET + zero regulated,
+ // 149/150 is zero FET + full regulated,
+ // so don't try to gradually adjust between
+ if ((RAMP_SIZE == actual_level) || (gt >= RAMP_SIZE-1)) {
+ set_level(gt + 1);
+ return true;
+ }
+
+ PWM_DATATYPE pwm1 = PWM_GET(pwm1_levels, gt);
+ GRADUAL_ADJUST_SIMPLE(pwm1, CH1_PWM);
+
+ if (pwm1 == CH1_PWM) return true; // done
+ return false; // not done yet
+}
+
diff --git a/hwdef-fw3x-lume1.h b/hwdef-fw3x-lume1.h
index f2e9141..c03248b 100644
--- a/hwdef-fw3x-lume1.h
+++ b/hwdef-fw3x-lume1.h
@@ -1,5 +1,5 @@
// lume1 Driver Rev B for FW3x driver layout (attiny1634)
-// Copyright (C) 2020-2023 (FIXME)
+// Copyright (C) 2020-2023 LoneOceans, Selene ToyKeeper
// SPDX-License-Identifier: GPL-3.0-or-later
#pragma once
@@ -8,9 +8,9 @@
*
* Pin / Name / Function in Lume1 Rev B
* 1 PA6 Regulated PWM (PWM1B)
- * 2 PA5 R red aux LED (PWM0B)
- * 3 PA4 G green aux LED
- * 4 PA3 B blue aux LED
+ * 2 PA5 R: red aux LED (PWM0B)
+ * 3 PA4 G: green aux LED
+ * 4 PA3 B: blue aux LED
* 5 PA2 e-switch (PCINT2)
* 6 PA1 Jumper 1
* 7 PA0 Jumper 2
@@ -30,36 +30,57 @@
* ADC12 internal thermal sensor (not used for lume1)
*
* Main LED power uses one pin as a global Buck Boost Enable, and
- * one pin to control the power level via PWM. Another pin is used
- * for FET control.
+ * one pin to control the power level via PWM.
+ * Another pin is used for DD FET control.
*/
-#ifdef ATTINY
-#undef ATTINY
-#endif
#define ATTINY 1634
#include <avr/io.h>
-#define PWM_CHANNELS 2
-// Added for Lume1 Buck Boost Driver
-#define PWM_BITS 10 // 0 to 1023 at 3.9 kHz, not 0 to 255 at 15.6 kHz
-#define PWM_TOP 1023
+#define HWDEF_C_FILE hwdef-fw3x-lume1.c
-#define SWITCH_PIN PA2 // pin 5
-#define SWITCH_PCINT PCINT2 // pin 5 pin change interrupt
-#define SWITCH_PCIE PCIE0 // PCIE0 is for PCINT[7:0]
-#define SWITCH_PCMSK PCMSK0 // PCMSK0 is for PCINT[7:0]
-#define SWITCH_PORT PINA // PINA or PINB or PINC
+// allow using aux LEDs as extra channel modes
+#include "chan-rgbaux.h"
+
+// channel modes:
+// * 0. main LEDs
+// * 1+. aux RGB
+#define NUM_CHANNEL_MODES (1 + NUM_RGB_AUX_CHANNEL_MODES)
+enum CHANNEL_MODES {
+ CM_MAIN = 0,
+ RGB_AUX_ENUMS
+};
+
+#define DEFAULT_CHANNEL_MODE CM_MAIN
-#define PWM1_PIN PA6 // pin 1, Buck Boost CTRL pin or 7135-eqv PWM
-#define PWM1_LVL OCR1B // OCR1A is the output compare register for PA6
+// right-most bit first, modes are in fedcba9876543210 order
+#define CHANNEL_MODES_ENABLED 0b0000000000000001
-#define PWM2_PIN PB3 // pin 16, FET PWM Pin, but only used as on (1023) or off (0)
-#define PWM2_LVL OCR1A // OCR1A is the output compare register for PB3
+
+#define PWM_CHANNELS 2 // old, remove this
// Added for Lume1 Buck Boost Driver
-#define LED_ENABLE_PIN PA7 // pin 20, BuckBoost Enable
-#define LED_ENABLE_PORT PORTA // control port for PA7
+#define PWM_BITS 16 // 0 to 1023 at 3.9 kHz, not 0 to 255 at 15.6 kHz
+#define PWM_GET PWM_GET16
+#define PWM_DATATYPE uint16_t
+#define PWM_DATATYPE2 uint32_t // only needs 32-bit if ramp values go over 255
+#define PWM1_DATATYPE uint16_t // regulated ramp
+#define PWM2_DATATYPE uint16_t // DD FET ramp
+
+// PWM parameters of both channels are tied together because they share a counter
+#define PWM_TOP ICR1 // holds the TOP value for variable-resolution PWM
+#define PWM_TOP_INIT 1023
+#define PWM_CNT TCNT1 // for dynamic PWM, reset phase
+
+// regulated channel
+#define CH1_PIN PA6 // pin 1, Buck Boost CTRL pin or 7135-eqv PWM
+#define CH1_PWM OCR1B // OCR1B is the output compare register for PA6
+#define CH1_ENABLE_PIN PA7 // pin 20, BuckBoost Enable
+#define CH1_ENABLE_PORT PORTA // control port for PA7
+
+// DD FET channel
+#define CH2_PIN PB3 // pin 16, FET PWM Pin, but only used as on (1023) or off (0)
+#define CH2_PWM OCR1A // OCR1A is the output compare register for PB3
/* // For Jumpers X1 to X4, no SW support yet
#define JUMPER1_PIN PA1
@@ -68,8 +89,17 @@
#define JUMPER4_PIN PC4
*/
-#define USE_VOLTAGE_DIVIDER // use a dedicated pin, not VCC, because VCC input is flattened
-#define VOLTAGE_PIN PB0 // Pin 19 PB0 ADC5
+// e-switch
+#define SWITCH_PIN PA2 // pin 5
+#define SWITCH_PCINT PCINT2 // pin 5 pin change interrupt
+#define SWITCH_PCIE PCIE0 // PCIE0 is for PCINT[7:0]
+#define SWITCH_PCMSK PCMSK0 // PCMSK0 is for PCINT[7:0]
+#define SWITCH_PORT PINA // PINA or PINB or PINC
+#define SWITCH_PUE PUEA // pullup group A
+#define PCINT_vect PCINT0_vect // ISR for PCINT[7:0]
+
+#define USE_VOLTAGE_DIVIDER // use a dedicated pin, not VCC, because VCC input is flattened
+#define VOLTAGE_PIN PB0 // Pin 19 PB0 ADC5
// pin to ADC mappings are in DS table 19-4
#define VOLTAGE_ADC ADC5D // digital input disable pin for PB1
// DIDR0/DIDR1 mappings are in DS section 19.13.5, 19.13.6
@@ -119,52 +149,54 @@
#define AUXLED_RGB_DDR DDRA // DDRA or DDRB or DDRC
#define AUXLED_RGB_PUE PUEA // PUEA or PUEB or PUEC
-// with so many pins, doing this all with #ifdefs gets awkward...
-// ... so just hardcode it in each hwdef file instead
// For lume1 driver, no SW support for Auxillary Jumpers X1 to X4 yet!
inline void hwdef_setup() {
- // enable output ports in Data Direction Registers
- // FET PWM Pin
- DDRB = (1 << PWM2_PIN);
- // Main PWM, Buck Boost Enable Pin, aux R/G/B
- DDRA = (1 << PWM1_PIN)
- | (1 << LED_ENABLE_PIN)
- | (1 << AUXLED_R_PIN)
- | (1 << AUXLED_G_PIN)
- | (1 << AUXLED_B_PIN)
- ;
- //DDRB&=~(1<<VOLTAGE_PIN); // All pins are input by default
- /* // For Jumpers X1 to X4, no SW support yet
- DDRA &= (1<<JUMPER1_PIN);
- DDRA &= (1<<JUMPER2_PIN);
- DDRC &= (1<<JUMPER3_PIN);
- DDRC &= (1<<JUMPER4_PIN);
- PUEA = (1 << JUMPER1_PIN);
- PUEA = (1 << JUMPER2_PIN);
- PUEC = (1 << JUMPER3_PIN);
- PUEC = (1 << JUMPER4_PIN);
- */
-
- // configure PWM for 10 bit at 3.9kHz
- // Setup PWM. F_pwm = F_clkio / 2 / N / TOP, where N = prescale factor, TOP = top of counter
- // pre-scale for timer: N = 1
- // WGM1[3:0]: 0,0,1,1: PWM, Phase Correct, 10-bit (DS table 12-5)
- // CS1[2:0]: 0,0,1: clk/1 (No prescaling) (DS table 12-6)
- // COM1A[1:0]: 1,0: PWM OC1A in the normal direction (DS table 12-4)
- // COM1B[1:0]: 1,0: PWM OC1B in the normal direction (DS table 12-4)
- TCCR1A = (1<<WGM11) | (1<<WGM10) // 10-bit (TOP=0x03FF) (DS table 12-5)
- | (1<<COM1A1) | (0<<COM1A0) // PWM 1A Clear OC1A on Compare Match
- | (1<<COM1B1) | (0<<COM1B0) // PWM 1B Clear OC1B on Compare Match
- ;
- TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6)
- | (0<<WGM13) | (0<<WGM12) // PWM, Phase Correct, 10-bit
- ;
-
- // set up e-switch
- //PORTA = (1 << SWITCH_PIN); // TODO: configure PORTA / PORTB / PORTC?
- PUEA = (1 << SWITCH_PIN); // pull-up for e-switch
- SWITCH_PCMSK = (1 << SWITCH_PCINT); // enable pin change interrupt
+ // enable output ports
+ // FET PWM Pin
+ DDRB = (1 << CH2_PIN);
+ // Main PWM, Buck Boost Enable Pin, aux R/G/B
+ DDRA = (1 << CH1_PIN)
+ | (1 << CH1_ENABLE_PIN)
+ | (1 << AUXLED_R_PIN)
+ | (1 << AUXLED_G_PIN)
+ | (1 << AUXLED_B_PIN)
+ ;
+
+ //DDRB&=~(1<<VOLTAGE_PIN); // All pins are input by default
+ /* // For Jumpers X1 to X4, no SW support yet
+ DDRA &= (1<<JUMPER1_PIN);
+ DDRA &= (1<<JUMPER2_PIN);
+ DDRC &= (1<<JUMPER3_PIN);
+ DDRC &= (1<<JUMPER4_PIN);
+ PUEA = (1 << JUMPER1_PIN);
+ PUEA = (1 << JUMPER2_PIN);
+ PUEC = (1 << JUMPER3_PIN);
+ PUEC = (1 << JUMPER4_PIN);
+ */
+
+ // configure PWM for 10 bit at 3.9kHz
+ // Setup PWM. F_pwm = F_clkio / 2 / N / TOP, where N = prescale factor, TOP = top of counter
+ // pre-scale for timer: N = 1
+ // WGM1[3:0]: 0,0,1,1: PWM, Phase Correct, 10-bit (DS table 12-5)
+ // CS1[2:0]: 0,0,1: clk/1 (No prescaling) (DS table 12-6)
+ // COM1A[1:0]: 1,0: PWM OC1A in the normal direction (DS table 12-4)
+ // COM1B[1:0]: 1,0: PWM OC1B in the normal direction (DS table 12-4)
+ TCCR1A = (1<<WGM11) | (1<<WGM10) // 10-bit (TOP=0x03FF) (DS table 12-5)
+ | (1<<COM1A1) | (0<<COM1A0) // PWM 1A Clear OC1A on Compare Match
+ | (1<<COM1B1) | (0<<COM1B0) // PWM 1B Clear OC1B on Compare Match
+ ;
+ TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6)
+ | (0<<WGM13) | (0<<WGM12) // PWM, Phase Correct, 10-bit
+ ;
+
+ // set PWM resolution
+ PWM_TOP = PWM_TOP_INIT;
+
+ // set up e-switch
+ SWITCH_PUE = (1 << SWITCH_PIN); // pull-up for e-switch
+ SWITCH_PCMSK = (1 << SWITCH_PCINT); // enable pin change interrupt
}
+
#define LAYOUT_DEFINED
diff --git a/hwdef-noctigon-kr4.c b/hwdef-noctigon-kr4.c
index b721bdc..884151d 100644
--- a/hwdef-noctigon-kr4.c
+++ b/hwdef-noctigon-kr4.c
@@ -1,7 +1,6 @@
// Noctigon KR4 PWM helper functions
// Copyright (C) 2020-2023 Selene ToyKeeper
// SPDX-License-Identifier: GPL-3.0-or-later
-
#pragma once
#include "chan-rgbaux.c"
diff --git a/hwdef-noctigon-kr4.h b/hwdef-noctigon-kr4.h
index b06411d..5570fb7 100644
--- a/hwdef-noctigon-kr4.h
+++ b/hwdef-noctigon-kr4.h
@@ -63,7 +63,7 @@ enum CHANNEL_MODES {
//#define CHANNEL_MODE_ARGS 0,0,0,0,0,0,0,0
-#define PWM_CHANNELS 2 // old, remove this
+#define PWM_CHANNELS 2 // old, remove this
#define PWM_BITS 16 // dynamic 16-bit, but never goes over 255
#define PWM_GET PWM_GET8
diff --git a/spaghetti-monster/anduril/cfg-fw3x-lume1.h b/spaghetti-monster/anduril/cfg-fw3x-lume1.h
index 280c433..184ab8e 100644
--- a/spaghetti-monster/anduril/cfg-fw3x-lume1.h
+++ b/spaghetti-monster/anduril/cfg-fw3x-lume1.h
@@ -1,5 +1,5 @@
// lume1 for FW3x config options for Anduril
-// Copyright (C) 2020-2023 (FIXME)
+// Copyright (C) 2020-2023 LoneOceans, Selene ToyKeeper
// SPDX-License-Identifier: GPL-3.0-or-later
#pragma once
@@ -11,10 +11,7 @@
* - 85: https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2586-AVR-8-bit-Microcontroller-ATtiny25-ATtiny45-ATtiny85_Datasheet.pdf
*/
-// TODO: determine if "03" (Lumintop) is the right prefix,
-// or if there should be a brand ID for LoneOceans
#define MODEL_NUMBER "0314"
-
#include "hwdef-fw3x-lume1.h"
// ATTINY: 1634
@@ -36,7 +33,7 @@
// ../../bin/level_calc.py cube 1 149 7135 0 0.5 1000, with 0 appended to the end.
// for FET PWM (PWM2), all values are 0, except for last value of 1023
// (with max_pwm set to 1023)
-#define RAMP_LENGTH 150
+#define RAMP_SIZE 150
//#define PWM1_LEVELS 0,0,0,0,1,1,1,1,2,2,2,3,3,4,4,5,5,6,7,7,8,9,10,11,12,13,14,15,16,17,19,20,22,23,25,26,28,30,32,34,36,38,40,42,45,47,49,52,55,58,60,63,66,70,73,76,80,83,87,91,94,98,102,107,111,115,120,124,129,134,139,144,150,155,160,166,172,178,184,190,196,203,209,216,223,230,237,244,252,259,267,275,283,291,299,308,316,325,334,343,353,362,372,382,392,402,412,423,433,444,455,466,478,489,501,513,525,538,550,563,576,589,602,616,630,644,658,672,687,701,716,731,747,762,778,794,810,827,844,861,878,895,913,930,948,967,985,1004,1023,0
#define PWM1_LEVELS 1,1,1,1,2,2,2,2,3,3,3,4,4,5,5,6,6,7,8,8,9,10,11,12,13,14,15,16,17,18,20,21,23,24,26,27,29,31,33,35,37,39,41,43,45,48,50,53,56,58,61,64,67,70,74,77,80,84,88,91,95,99,103,108,112,116,121,125,130,135,140,145,150,156,161,167,173,178,184,191,197,203,210,217,223,230,238,245,252,260,268,275,283,292,300,308,317,326,335,344,353,363,372,382,392,402,413,423,434,445,456,467,478,490,502,514,526,538,551,563,576,589,603,616,630,644,658,672,687,702,717,732,747,763,778,794,811,827,844,861,878,895,913,931,949,967,985,1004,1023,0
#define PWM2_LEVELS 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1023
@@ -67,25 +64,18 @@
#define RAMP_DISCRETE_CEIL RAMP_SMOOTH_CEIL
#define RAMP_DISCRETE_STEPS 7
-// Muggle mode: Goal from about ~10 lumens to about ~300+ lumens
-// In this case, ramp number 99 is about 1A to the driver
-#define MUGGLE_FLOOR RAMP_DISCRETE_FLOOR
-#define MUGGLE_CEILING 99
+#define SIMPLE_UI_FLOOR RAMP_DISCRETE_FLOOR
+#define SIMPLE_UI_CEIL 120
+#define SIMPLE_UI_STEPS 5
// slow down party strobe; this driver can't pulse for too short a time
#define PARTY_STROBE_ONTIME 4
-// optional, makes initial turbo step-down faster so first peak isn't as hot
-// FET mode can run very very hot, so be extra careful
-//#define THERM_HARD_TURBO_DROP
-
// stop panicking at ~85% regulated power or ~750 lm
#define THERM_FASTER_LEVEL 140
#define THERM_CAL_OFFSET 0 // not needed due to external sensor
-// easier access to thermal config mode, similar to Emisar, Noctigon
-#define USE_TENCLICK_THERMAL_CONFIG
-
// can't reset the normal way because power is connected before the button
#define USE_SOFT_FACTORY_RESET
+
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-28 19:50:05 +0000