diff options
Diffstat (limited to 'hw/sofirn/sp10-pro')
| -rw-r--r-- | hw/sofirn/sp10-pro/cfg.h | 81 | ||||
| -rw-r--r-- | hw/sofirn/sp10-pro/hwdef.c | 63 | ||||
| -rw-r--r-- | hw/sofirn/sp10-pro/hwdef.h | 157 |
3 files changed, 301 insertions, 0 deletions
diff --git a/hw/sofirn/sp10-pro/cfg.h b/hw/sofirn/sp10-pro/cfg.h new file mode 100644 index 0000000..0e2f28d --- /dev/null +++ b/hw/sofirn/sp10-pro/cfg.h @@ -0,0 +1,81 @@ +// Sofirn SP10 Pro config options for Anduril +// Copyright (C) 2022-2023 (original author TBD), Selene ToyKeeper +// SPDX-License-Identifier: GPL-3.0-or-later +#pragma once + +#define MODEL_NUMBER "0631" +#include "hwdef-sofirn-sp10-pro.h" +// ATTINY: 1616 + +// 1....15: level_calc.py 3.01 1 15 7135 1 0.1 2 --pwm dyn:15:64:64 +// 16..150: level_calc.py 5.01 1 135 7135 1 2 800 --pwm dyn:49:3072:255:3.0 +#define RAMP_SIZE 150 +#define _PWM1_LEVELS_ 1, 2, 4, 6, 9,12,15,19,23,28,34,41,48,55,64 +#define _PWM1_TOPS_ 64,64,64,64,64,64,64,64,64,64,64,64,64,64,64 +#define _PWM2_LEVELS_ 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 10, 10, 10, 11, 11, 12, 13, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, 34, 35, 37, 38, 39, 41, 42, 44, 46, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 70, 72, 74, 77, 79, 82, 85, 88, 90, 93, 96, 99,103,106,109,113,116,120,123,127,131,135,139,143,147,151,156,160,165,170,175,180,185,190,195,201,206,212,218,223,230,236,242,248,255 +#define _PWM2_TOPS_ 3072,1960,2372,1476,2097,1572,1920,1570,1777,1524,1646,1454,1286,1369,1234,1115,1011,918,837,894,823,759,702,650,603,560,522,487,455,425,398,374,351,330,310,292,275,259,280,265,251,266,253,240,252,240,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255 +#define PWM1_LEVELS _PWM1_LEVELS_,_PWM2_TOPS_ +#define PWM2_LEVELS 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,_PWM2_LEVELS_ +#define PWM_TOPS _PWM1_TOPS_,_PWM2_TOPS_ + +#define MAX_1x7135 15 +#define HALFSPEED_LEVEL 15 +#define QUARTERSPEED_LEVEL 15 +#define DEFAULT_LEVEL 50 + +#define RAMP_SMOOTH_FLOOR 1 +#define RAMP_SMOOTH_CEIL 150 +// 1 25 50 [75] 100 125 150 +#define RAMP_DISCRETE_FLOOR 1 +#define RAMP_DISCRETE_CEIL RAMP_SMOOTH_CEIL +#define RAMP_DISCRETE_STEPS 7 + +// at Sofirn's request, use max (150) for the Simple UI ceiling +// 15 48 [82] 116 150 +#define SIMPLE_UI_FLOOR MAX_1x7135 +#define SIMPLE_UI_CEIL 150 +#define SIMPLE_UI_STEPS 5 + +// turn on at ~6 lm by default (level 50/150, or ramp step 2/5 or 3/7) +// (also sets lockout mode 2H to a useful level) +#define DEFAULT_MANUAL_MEMORY 50 +// reset to default after being off for 10 minutes +#define DEFAULT_MANUAL_MEMORY_TIMER 10 + +// enable SOS in the blinkies group +#define USE_SOS_MODE +#define USE_SOS_MODE_IN_BLINKY_GROUP + +// Allow 3C in Simple UI for switching between smooth and stepped ramping +#define USE_SIMPLE_UI_RAMPING_TOGGLE + +// and finally, set the default ramp style to Stepped +#undef RAMP_STYLE +#define RAMP_STYLE 1 // 0 = smooth, 1 = stepped + +// stop panicking at ~30% power +#define THERM_FASTER_LEVEL 105 +#define MIN_THERM_STEPDOWN 65 // must be > end of dynamic PWM range + +// slow down party strobe; this driver can't pulse for too short a time +//#define PARTY_STROBE_ONTIME 8 +#define STROBE_OFF_LEVEL 1 // keep the regulator chip on between pulses + +// the default of 26 looks a bit flat, so increase it +#define CANDLE_AMPLITUDE 50 + +// enable 2 click turbo (replaces USE_2C_MAX_TURBO) +#define DEFAULT_2C_STYLE 1 + +// don't blink during the ramp or at the ceiling +#ifdef BLINK_AT_RAMP_MIDDLE +#undef BLINK_AT_RAMP_MIDDLE +#endif +#ifdef BLINK_AT_RAMP_CEIL +#undef BLINK_AT_RAMP_CEIL +#endif + + +// enable factory reset on 13H without loosening tailcap +#define USE_SOFT_FACTORY_RESET + diff --git a/hw/sofirn/sp10-pro/hwdef.c b/hw/sofirn/sp10-pro/hwdef.c new file mode 100644 index 0000000..42844a7 --- /dev/null +++ b/hw/sofirn/sp10-pro/hwdef.c @@ -0,0 +1,63 @@ +// Sofirn SP10 Pro PWM helper functions +// Copyright (C) 2023 Selene ToyKeeper +// SPDX-License-Identifier: GPL-3.0-or-later +#pragma once + +void set_level_zero(); + +void set_level_main(uint8_t level); +bool gradual_tick_main(uint8_t gt); + + +Channel channels[] = { + { // main LEDs + .set_level = set_level_main, + .gradual_tick = gradual_tick_main + }, +}; + + +void set_level_zero() { + CH1_PWM = 0; + CH2_PWM = 0; + PWM_CNT = 0; // reset phase + BST_ENABLE_PORT &= ~(1 << BST_ENABLE_PIN); // boost off +} + +// single set of LEDs with 2 stacked power channels +void set_level_main(uint8_t level) { + PWM_DATATYPE ch1_pwm = PWM_GET(pwm1_levels, level); + PWM_DATATYPE ch2_pwm = PWM_GET(pwm2_levels, level); + // pulse frequency modulation, a.k.a. dynamic PWM + uint16_t top = PWM_GET16(pwm_tops, level); + + BST_ENABLE_PORT |= (1 << BST_ENABLE_PIN); // boost on + + CH1_PWM = ch1_pwm; + CH2_PWM = ch2_pwm; + PWM_TOP = top; + + // force reset phase when turning on from zero + // (because otherwise the initial response is inconsistent) + if (! actual_level) PWM_CNT = 0; +} + +bool gradual_tick_main(uint8_t gt) { + PWM_DATATYPE pwm1 = PWM_GET(pwm1_levels, gt); + PWM_DATATYPE pwm2 = PWM_GET(pwm2_levels, gt); + + // ch1 sometimes makes huge leaps; don't make it gradual + // if either current or new level is in the leap zone, just leap + if ((CH1_PWM + pwm1) > 128) CH1_PWM = pwm1; + else GRADUAL_ADJUST_SIMPLE(pwm1, CH1_PWM); + + GRADUAL_ADJUST_SIMPLE(pwm2, CH2_PWM); + + if ( (pwm1 == CH1_PWM) + && (pwm2 == CH2_PWM) + ) { + return true; // done + } + return false; // not done yet +} + diff --git a/hw/sofirn/sp10-pro/hwdef.h b/hw/sofirn/sp10-pro/hwdef.h new file mode 100644 index 0000000..5cef6a7 --- /dev/null +++ b/hw/sofirn/sp10-pro/hwdef.h @@ -0,0 +1,157 @@ +// Sofirn SP10 Pro pinout +// Copyright (C) 2022-2023 (original author TBD), Selene ToyKeeper +// SPDX-License-Identifier: GPL-3.0-or-later +#pragma once + +/* + * ATTINY1616 Mapping: + * PB5 : PWM small channel (TCA0 - WO2 Alternate MUX) + * PB3 : eSwitch + * PB0 : PWM big channel (TCA0 - WO0) + * PB4 : Voltage divider (ADC0 - AIN9) + * PA1 : Boost Enable + */ + +#define ATTINY 1616 +#include <avr/io.h> + +#define HWDEF_C_FILE hwdef-sofirn-sp10-pro.c + +// channel modes: +// * 0. low+high PWM stacked +#define NUM_CHANNEL_MODES 1 +enum CHANNEL_MODES { + CM_MAIN = 0, +}; + +#define DEFAULT_CHANNEL_MODE CM_MAIN + +// right-most bit first, modes are in fedcba9876543210 order +#define CHANNEL_MODES_ENABLED 0b00000001 + + +#define PWM_CHANNELS 2 // old, remove this + +#define PWM_BITS 16 // data type needs 16 bits, not 8 +#define PWM_GET PWM_GET16 +#define PWM_DATATYPE uint16_t // is used for PWM_TOPS (which goes way over 255) +#define PWM_DATATYPE2 uint32_t // only needs 32-bit if ramp values go over 255 +#define PWM1_DATATYPE uint16_t // low PWM ramp +#define PWM2_DATATYPE uint16_t // high PWM ramp + +// PWM parameters of both channels are tied together because they share a counter +#define PWM_TOP TCA0.SINGLE.PERBUF // holds the TOP value for for variable-resolution PWM +#define PWM_CNT TCA0.SINGLE.CNT // for resetting phase after each TOP adjustment +#define PWM_TOP_INIT 255 // highest value used in top half of ramp (unused?) + +// Small channel +#define CH1_PIN PB5 +#define CH1_PWM TCA0.SINGLE.CMP2BUF // PB5 is Alternate MUX for TCA Compare 2 + +// Big channel +#define CH2_PIN PB0 +#define CH2_PWM TCA0.SINGLE.CMP0BUF // PB0 is TCA Compare 0 + +// boost enable +#define BST_ENABLE_PIN PIN1_bp +#define BST_ENABLE_PORT PORTA_OUT + +// e-switch +#define SWITCH_PIN 3 +#define SWITCH_PORT VPORTB.IN +#define SWITCH_ISC_REG PORTB.PIN3CTRL +#define SWITCH_VECT PORTB_PORT_vect +#define SWITCH_INTFLG VPORTB.INTFLAGS +#define SWITCH_PCINT PCINT0 +#define PCINT_vect PCINT0_vect // ISR for PCINT[7:0] + +// Voltage divider battLVL +#define USE_VOLTAGE_DIVIDER // use a dedicated pin, not VCC, because VCC input is regulated +#define DUAL_VOLTAGE_FLOOR 21 // for AA/14500 boost drivers, don't indicate low voltage if below this level +#define DUAL_VOLTAGE_LOW_LOW 7 // the lower voltage range's danger zone 0.7 volts (NiMH) +#define ADMUX_VOLTAGE_DIVIDER ADC_MUXPOS_AIN9_gc // which ADC channel to read + +// Raw ADC readings at 4.4V and 2.2V +// calibrate the voltage readout here +// estimated / calculated values are: +// (voltage - D1) * (R2/(R2+R1) * 1024 / 1.1) +// Resistors are 300,000 and 100,000 +#ifndef ADC_44 +#define ADC_44 1023 // raw value at 4.40V +#endif +#ifndef ADC_22 +#define ADC_22 512 // raw value at 2.20V +#endif + + + +inline void hwdef_setup() { + + // set up the system clock to run at 10 MHz instead of the default 3.33 MHz + _PROTECTED_WRITE( CLKCTRL.MCLKCTRLB, + CLKCTRL_PDIV_2X_gc | CLKCTRL_PEN_bm ); + + VPORTA.DIR = PIN1_bm; // Boost enable pin + VPORTB.DIR = PIN0_bm // big PWM channel + | PIN5_bm; // small PWM channel + //VPORTC.DIR = ...; + + // enable pullups on the input pins to reduce power + PORTA.PIN0CTRL = PORT_PULLUPEN_bm; + //PORTA.PIN1CTRL = PORT_PULLUPEN_bm; // Boost enable pin + PORTA.PIN2CTRL = PORT_PULLUPEN_bm; + PORTA.PIN3CTRL = PORT_PULLUPEN_bm; + PORTA.PIN4CTRL = PORT_PULLUPEN_bm; + PORTA.PIN5CTRL = PORT_PULLUPEN_bm; + PORTA.PIN6CTRL = PORT_PULLUPEN_bm; + PORTA.PIN7CTRL = PORT_PULLUPEN_bm; + + //PORTB.PIN0CTRL = PORT_PULLUPEN_bm; // Big PWM channel + PORTB.PIN1CTRL = PORT_PULLUPEN_bm; + PORTB.PIN2CTRL = PORT_PULLUPEN_bm; + PORTB.PIN3CTRL = PORT_PULLUPEN_bm + | PORT_ISC_BOTHEDGES_gc; // e-switch + //PORTB.PIN4CTRL = PORT_PULLUPEN_bm; // Voltage divider + //PORTB.PIN5CTRL = PORT_PULLUPEN_bm; // Small PWM channel + + PORTC.PIN0CTRL = PORT_PULLUPEN_bm; + PORTC.PIN1CTRL = PORT_PULLUPEN_bm; + PORTC.PIN2CTRL = PORT_PULLUPEN_bm; + PORTC.PIN3CTRL = PORT_PULLUPEN_bm; + + // set up the PWM + // https://ww1.microchip.com/downloads/en/DeviceDoc/ATtiny1614-16-17-DataSheet-DS40002204A.pdf + // PB0 is TCA0:WO0, use TCA_SINGLE_CMP0EN_bm + // PB1 is TCA0:WO1, use TCA_SINGLE_CMP1EN_bm + // PB2 is TCA0:WO2, use TCA_SINGLE_CMP2EN_bm + // For Fast (Single Slope) PWM use TCA_SINGLE_WGMODE_SINGLESLOPE_gc + // For Phase Correct (Dual Slope) PWM use TCA_SINGLE_WGMODE_DSBOTTOM_gc + // See the manual for other pins, clocks, configs, portmux, etc + PORTMUX.CTRLC = PORTMUX_TCA02_ALTERNATE_gc; // Use alternate pin for TCA0:WO2 + TCA0.SINGLE.CTRLB = TCA_SINGLE_CMP0EN_bm + | TCA_SINGLE_CMP2EN_bm + | TCA_SINGLE_WGMODE_DSBOTTOM_gc; + PWM_TOP = PWM_TOP_INIT; + TCA0.SINGLE.CTRLA = TCA_SINGLE_CLKSEL_DIV1_gc + | TCA_SINGLE_ENABLE_bm; +} + + +// set fuses, these carry over to the ELF file +// we need this for enabling BOD in Active Mode from the factory. +// settings can be verified / dumped from the ELF file using this +// command: avr-objdump -d -S -j .fuse anduril.elf +FUSES = { + .WDTCFG = FUSE_WDTCFG_DEFAULT, // Watchdog Configuration + .BODCFG = FUSE_ACTIVE0, // BOD Configuration + .OSCCFG = FUSE_OSCCFG_DEFAULT, // Oscillator Configuration + .TCD0CFG = FUSE_TCD0CFG_DEFAULT, // TCD0 Configuration + .SYSCFG0 = FUSE_SYSCFG0_DEFAULT, // System Configuration 0 + .SYSCFG1 = FUSE_SYSCFG1_DEFAULT, // System Configuration 1 + .APPEND = FUSE_APPEND_DEFAULT, // Application Code Section End + .BOOTEND = FUSE_BOOTEND_DEFAULT, // Boot Section End +}; + + +#define LAYOUT_DEFINED + |