diff options
Diffstat (limited to '')
| -rw-r--r-- | hwdef-emisar-d4k-3ch.c | 1 | ||||
| -rw-r--r-- | hwdef-emisar-d4k-3ch.h | 2 | ||||
| -rw-r--r-- | hwdef-noctigon-m44.c | 190 | ||||
| -rw-r--r-- | hwdef-noctigon-m44.h | 43 |
4 files changed, 149 insertions, 87 deletions
diff --git a/hwdef-emisar-d4k-3ch.c b/hwdef-emisar-d4k-3ch.c index 58e9b35..ba6643d 100644 --- a/hwdef-emisar-d4k-3ch.c +++ b/hwdef-emisar-d4k-3ch.c @@ -262,6 +262,7 @@ void set_level_auto3(uint8_t level) { } ///// "gradual tick" functions for smooth thermal regulation ///// +// (and other smooth adjustments) bool gradual_adjust(PWM_DATATYPE main2, PWM_DATATYPE led3, PWM_DATATYPE led4) { // adjust multiple times based on current brightness diff --git a/hwdef-emisar-d4k-3ch.h b/hwdef-emisar-d4k-3ch.h index 59e6f01..581f51c 100644 --- a/hwdef-emisar-d4k-3ch.h +++ b/hwdef-emisar-d4k-3ch.h @@ -27,8 +27,6 @@ * 20 PA7 e-switch (PCINT7) * ADC12 thermal sensor * - * All 3 channels share a single Opamp enable pin, - * but have individual PWM controls. * PWM speed + resolution is dynamic on 2 channels, * and 8-bit 16 kHz on 1 channel. * diff --git a/hwdef-noctigon-m44.c b/hwdef-noctigon-m44.c index 776cb82..0b7f027 100644 --- a/hwdef-noctigon-m44.c +++ b/hwdef-noctigon-m44.c @@ -1,7 +1,6 @@ // hwdef for Noctigon M44 2-channel light // Copyright (C) 2023 Selene ToyKeeper // SPDX-License-Identifier: GPL-3.0-or-later - #pragma once #include "chan-rgbaux.c" @@ -52,20 +51,39 @@ Channel channels[] = { }; +void set_level_zero() { + // disable timer 1 overflow interrupt + // (helps improve button press handling from Off state) + TIMSK &= ~(1 << TOIE1); + + // turn off all LEDs + ch1_dsm_lvl = 0; + ch2_dsm_lvl = 0; + CH1_PWM = 0; + CH2_PWM = 0; + PWM_CNT = 0; + CH1_ENABLE_PORT &= ~(1 << CH1_ENABLE_PIN); // disable opamp + CH2_ENABLE_PORT &= ~(1 << CH2_ENABLE_PIN); // disable opamp +} + + +// wrap setting the dsm vars, to get a faster response +// (just setting *_dsm_lvl doesn't work well for strobes) // set new values for both channels, // handling any possible combination // and any before/after state -void set_pwms(uint16_t ch1_pwm, uint16_t ch2_pwm, uint16_t top, - uint8_t ch1_on, uint8_t ch2_on) { +void set_hw_levels(PWM_DATATYPE ch1, PWM_DATATYPE ch2, + bool ch1_on, bool ch2_on) { bool was_on = (CH1_PWM>0) || (CH2_PWM>0) || ( CH1_ENABLE_PORT & (1 << CH1_ENABLE_PIN) ) || ( CH2_ENABLE_PORT & (1 << CH2_ENABLE_PIN) ); - bool now_on = (ch1_pwm>0) || (ch2_pwm>0) || ch1_on || ch2_on; + //bool now_on = (ch1>0) || (ch2>0) || ch1_on || ch2_on; + #if 0 // not needed any more, after switching to PWM+DSM // phase-correct PWM at zero (for flicker-free moon), // fast PWM otherwise - if (ch1_pwm || ch2_pwm) + if (ch1 || ch2) TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6) | (1<<WGM13) | (1<<WGM12) // fast adjustable PWM (DS table 12-5) //| (1<<WGM13) | (0<<WGM12) // phase-correct adjustable PWM (DS table 12-5) @@ -75,136 +93,170 @@ void set_pwms(uint16_t ch1_pwm, uint16_t ch2_pwm, uint16_t top, //| (1<<WGM13) | (1<<WGM12) // fast adjustable PWM (DS table 12-5) | (1<<WGM13) | (0<<WGM12) // phase-correct adjustable PWM (DS table 12-5) ; + #endif - if (ch1_pwm || ch1_on) + if (ch1 || ch1_on) CH1_ENABLE_PORT |= (1 << CH1_ENABLE_PIN); // enable opamp else CH1_ENABLE_PORT &= ~(1 << CH1_ENABLE_PIN); // disable opamp - if (ch2_pwm || ch2_on) + if (ch2 || ch2_on) CH2_ENABLE_PORT |= (1 << CH2_ENABLE_PIN); // enable opamp else CH2_ENABLE_PORT &= ~(1 << CH2_ENABLE_PIN); // disable opamp - CH1_PWM = ch1_pwm; - CH2_PWM = ch2_pwm; + // set delta-sigma soft levels + ch1_dsm_lvl = ch1; + ch2_dsm_lvl = ch2; + // set hardware PWM levels and init dsm loop + CH1_PWM = ch1_pwm = ch1 >> 7; + CH2_PWM = ch2_pwm = ch2 >> 7; + + #if 0 // not needed any more, after switching to PWM+DSM // manual phase sync when changing level while already on if (was_on && now_on) while(PWM_CNT > (top - 32)) {} PWM_TOP = top; + #endif + + // enable timer 1 overflow interrupt so DSM can work + TIMSK |= (1 << TOIE1); // reset phase when turning on or off //if ((! was_on) | (! now_on)) PWM_CNT = 0; if (! was_on) PWM_CNT = 0; + } -void set_level_zero() { - CH1_PWM = 0; - CH2_PWM = 0; - PWM_TOP = PWM_TOP_INIT; - PWM_CNT = 0; - CH1_ENABLE_PORT &= ~(1 << CH1_ENABLE_PIN); // disable opamp - CH2_ENABLE_PORT &= ~(1 << CH2_ENABLE_PIN); // disable opamp +// delta-sigma modulation of PWM outputs +// happens on each Timer0 overflow (every 512 cpu clock cycles) +// uses 8-bit pwm w/ 7-bit dsm (0b 0PPP PPPP PDDD DDDD) +ISR(TIMER1_OVF_vect) { + // set new hardware values first, + // for best timing (reduce effect of interrupt jitter) + CH1_PWM = ch1_pwm; + CH2_PWM = ch2_pwm; + + // calculate next values, now that timing matters less + + // accumulate error + ch1_dsm += (ch1_dsm_lvl & 0x007f); + // next PWM = base PWM value + carry bit + ch1_pwm = (ch1_dsm_lvl >> 7) + (ch1_dsm > 0x7f); + // clear carry bit + ch1_dsm &= 0x7f; + + // repeat for other channels + + ch2_dsm += (ch2_dsm_lvl & 0x007f); + ch2_pwm = (ch2_dsm_lvl >> 7) + (ch2_dsm > 0x7f); + ch2_dsm &= 0x7f; } + void set_level_ch1(uint8_t level) { - uint16_t pwm = PWM_GET(pwm1_levels, level); - uint16_t top = PWM_GET(pwm_tops, level); - set_pwms(pwm, 0, top, 1, 0); + PWM_DATATYPE pwm = PWM_GET(pwm1_levels, level); + set_hw_levels(pwm, 0, + 1, 0); } void set_level_ch2(uint8_t level) { - uint16_t pwm = PWM_GET(pwm1_levels, level); - uint16_t top = PWM_GET(pwm_tops, level); - set_pwms(0, pwm, top, 0, 1); + PWM_DATATYPE pwm = PWM_GET(pwm1_levels, level); + set_hw_levels(0, pwm, + 0, 1); } void set_level_both(uint8_t level) { - uint16_t pwm = PWM_GET(pwm1_levels, level); - uint16_t top = PWM_GET(pwm_tops, level); - set_pwms(pwm, pwm, top, 1, 1); + PWM_DATATYPE pwm = PWM_GET(pwm1_levels, level); + set_hw_levels(pwm, pwm, + 1, 1); } -void set_level_blend(uint8_t level) { - PWM_DATATYPE ch1_pwm, ch2_pwm; +void blend_helper(PWM_DATATYPE *warm, PWM_DATATYPE *cool, uint8_t level) { PWM_DATATYPE brightness = PWM_GET(pwm1_levels, level); - PWM_DATATYPE top = PWM_GET(pwm_tops, level); - uint8_t blend = cfg.channel_mode_args[channel_mode]; + uint8_t blend; + if (channel_mode == CM_AUTO) { + blend = 255 * (uint16_t)level / RAMP_SIZE; + if (cfg.channel_mode_args[channel_mode] & 0b01000000) + blend = 255 - blend; + } else { + blend = cfg.channel_mode_args[channel_mode]; + } - calc_2ch_blend(&ch1_pwm, &ch2_pwm, brightness, top, blend); + calc_2ch_blend(warm, cool, brightness, DSM_TOP, blend); +} +void set_level_blend(uint8_t level) { + PWM_DATATYPE warm, cool; + uint8_t blend = cfg.channel_mode_args[channel_mode]; + blend_helper(&warm, &cool, level); // don't turn off either emitter entirely while using middle blends - set_pwms(ch1_pwm, ch2_pwm, top, - blend < 255, blend > 0); + set_hw_levels(warm, cool, + blend < 255, blend > 0); } void set_level_auto(uint8_t level) { - PWM_DATATYPE ch1_pwm, ch2_pwm; - PWM_DATATYPE brightness = PWM_GET(pwm1_levels, level); - PWM_DATATYPE top = PWM_GET(pwm_tops, level); - uint8_t blend = 255 * (uint16_t)level / RAMP_SIZE; - if (cfg.channel_mode_args[channel_mode] & 0b01000000) - blend = 255 - blend; - - calc_2ch_blend(&ch1_pwm, &ch2_pwm, brightness, top, blend); - + PWM_DATATYPE warm, cool; + blend_helper(&warm, &cool, level); // don't turn off either emitter entirely // (it blinks pretty bright when the regulator turns on mid-ramp) - set_pwms(ch1_pwm, ch2_pwm, top, 1, 1); + set_hw_levels(warm, cool, + 1, 1); } +///// "gradual tick" functions for smooth thermal regulation ///// +// (and other smooth adjustments) ///// bump each channel toward a target value ///// -bool gradual_adjust(uint16_t ch1_pwm, uint16_t ch2_pwm) { - GRADUAL_ADJUST_SIMPLE(ch1_pwm, CH1_PWM); - GRADUAL_ADJUST_SIMPLE(ch2_pwm, CH2_PWM); +bool gradual_adjust(PWM_DATATYPE ch1, PWM_DATATYPE ch2) { + // adjust multiple times based on current brightness + // (so it adjusts faster/coarser when bright, slower/finer when dim) + + // higher shift = slower/finer adjustments + const uint8_t shift = 9; // ((255 << 7) >> 9) = 63 max + uint8_t steps; + + steps = ch1_dsm_lvl >> shift; + for (uint8_t i=0; i<=steps; i++) + GRADUAL_ADJUST_SIMPLE(ch1, ch1_dsm_lvl); + + steps = ch2_dsm_lvl >> shift; + for (uint8_t i=0; i<=steps; i++) + GRADUAL_ADJUST_SIMPLE(ch2, ch2_dsm_lvl); - // check for completion - if ((ch1_pwm == CH1_PWM) - && (ch2_pwm == CH2_PWM)) { + if ((ch1 == ch1_dsm_lvl) + && (ch2 == ch2_dsm_lvl )) { return true; // done } return false; // not done yet } bool gradual_tick_ch1(uint8_t gt) { - uint16_t pwm = PWM_GET(pwm1_levels, gt); + PWM_DATATYPE pwm = PWM_GET(pwm1_levels, gt); return gradual_adjust(pwm, 0); } bool gradual_tick_ch2(uint8_t gt) { - uint16_t pwm = PWM_GET(pwm1_levels, gt); + PWM_DATATYPE pwm = PWM_GET(pwm1_levels, gt); return gradual_adjust(0, pwm); } bool gradual_tick_both(uint8_t gt) { - uint16_t pwm = PWM_GET(pwm1_levels, gt); + PWM_DATATYPE pwm = PWM_GET(pwm1_levels, gt); return gradual_adjust(pwm, pwm); } bool gradual_tick_blend(uint8_t gt) { - PWM_DATATYPE ch1_pwm, ch2_pwm; - PWM_DATATYPE brightness = PWM_GET(pwm1_levels, gt); - PWM_DATATYPE top = PWM_GET(pwm_tops, gt); - uint8_t blend = cfg.channel_mode_args[channel_mode]; - - calc_2ch_blend(&ch1_pwm, &ch2_pwm, brightness, top, blend); - - return gradual_adjust(ch1_pwm, ch2_pwm); + PWM_DATATYPE warm, cool; + blend_helper(&warm, &cool, gt); + return gradual_adjust(warm, cool); } bool gradual_tick_auto(uint8_t gt) { - PWM_DATATYPE ch1_pwm, ch2_pwm; - PWM_DATATYPE brightness = PWM_GET(pwm1_levels, gt); - PWM_DATATYPE top = PWM_GET(pwm_tops, gt); - uint8_t blend = 255 * (uint16_t)gt / RAMP_SIZE; - if (cfg.channel_mode_args[channel_mode] & 0b01000000) - blend = 255 - blend; - - calc_2ch_blend(&ch1_pwm, &ch2_pwm, brightness, top, blend); - - return gradual_adjust(ch1_pwm, ch2_pwm); + PWM_DATATYPE warm, cool; + blend_helper(&warm, &cool, gt); + return gradual_adjust(warm, cool); } diff --git a/hwdef-noctigon-m44.h b/hwdef-noctigon-m44.h index d02d8dd..2a9198a 100644 --- a/hwdef-noctigon-m44.h +++ b/hwdef-noctigon-m44.h @@ -63,34 +63,41 @@ enum channel_modes_e { #define USE_CALC_2CH_BLEND -#define PWM_CHANNELS 1 // old, remove this +#define PWM_CHANNELS 1 // old, remove this -#define PWM_BITS 16 // 0 to 16383 at variable Hz, not 0 to 255 at 16 kHz +#define PWM_BITS 16 // 0 to 16383 at variable Hz, not 0 to 255 at 16 kHz #define PWM_GET PWM_GET16 #define PWM_DATATYPE uint16_t #define PWM_DATATYPE2 uint32_t // only needs 32-bit if ramp values go over 255 -#define PWM1_DATATYPE uint16_t // regular ramp table +#define PWM1_DATATYPE uint16_t // 15-bit PWM+DSM ramp //#define PWM2_DATATYPE uint16_t // max "200% power" ramp table -//#define PWM3_DATATYPE uint16_t // PWM_TOPs for 2nd ramp table // PWM parameters of both channels are tied together because they share a counter +// dynamic PWM #define PWM_TOP ICR1 // holds the TOP value for for variable-resolution PWM -#define PWM_TOP_INIT 511 -#define PWM_CNT TCNT1 // for dynamic PWM, reset phase - -#define CH1_PIN PB3 // pin 16, Opamp reference -#define CH1_PWM OCR1A // OCR1A is the output compare register for PB3 +#define PWM_TOP_INIT 255 +#define PWM_CNT TCNT1 // for checking / resetting phase +// (max is (255 << 7), because it's 8-bit PWM plus 7 bits of DSM) +#define DSM_TOP (255<<7) // 15-bit resolution leaves 1 bit for carry + +// 1st channel (8 LEDs) +uint16_t ch1_dsm_lvl; +uint8_t ch1_pwm, ch1_dsm; +#define CH1_PIN PB3 // pin 16, Opamp reference +#define CH1_PWM OCR1A // OCR1A is the output compare register for PB3 #define CH1_ENABLE_PIN PB0 // pin 19, Opamp power #define CH1_ENABLE_PORT PORTB // control port for PB0 -#define CH2_PIN PA6 // pin 1, 2nd LED Opamp reference -#define CH2_PWM OCR1B // OCR1B is the output compare register for PA6 +// 2nd channel (8 LEDs) +uint16_t ch2_dsm_lvl; +uint8_t ch2_pwm, ch2_dsm; +#define CH2_PIN PA6 // pin 1, 2nd LED Opamp reference +#define CH2_PWM OCR1B // OCR1B is the output compare register for PA6 #define CH2_ENABLE_PIN PA0 // pin 7, Opamp power #define CH2_ENABLE_PORT PORTA // control port for PA0 // e-switch -#ifndef SWITCH_PIN #define SWITCH_PIN PA7 // pin 20 #define SWITCH_PCINT PCINT7 // pin 20 pin change interrupt #define SWITCH_PCIE PCIE0 // PCIE1 is for PCINT[7:0] @@ -98,7 +105,6 @@ enum channel_modes_e { #define SWITCH_PORT PINA // PINA or PINB or PINC #define SWITCH_PUE PUEA // pullup group A #define PCINT_vect PCINT0_vect // ISR for PCINT[7:0] -#endif #define USE_VOLTAGE_DIVIDER // use a dedicated pin, not VCC, because VCC input is flattened #define VOLTAGE_PIN PB1 // Pin 18 / PB1 / ADC6 @@ -161,7 +167,7 @@ inline void hwdef_setup() { // configure PWM // Setup PWM. F_pwm = F_clkio / 2 / N / TOP, where N = prescale factor, TOP = top of counter // pre-scale for timer: N = 1 - // Linear opamp PWM for both main and 2nd LEDs (10-bit) + // PWM for both channels // WGM1[3:0]: 1,0,1,0: PWM, Phase Correct, adjustable (DS table 12-5) // WGM1[3:0]: 1,1,1,0: PWM, Fast, adjustable (DS table 12-5) // CS1[2:0]: 0,0,1: clk/1 (No prescaling) (DS table 12-6) @@ -172,17 +178,22 @@ inline void hwdef_setup() { | (1<<COM1B1) | (0<<COM1B0) // PWM 1B in normal direction (DS table 12-4) ; TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6) - | (1<<WGM13) | (1<<WGM12) // fast adjustable PWM (DS table 12-5) - //| (1<<WGM13) | (0<<WGM12) // phase-correct adjustable PWM (DS table 12-5) + //| (1<<WGM13) | (1<<WGM12) // fast adjustable PWM (DS table 12-5) + | (1<<WGM13) | (0<<WGM12) // phase-correct adjustable PWM (DS table 12-5) ; // set PWM resolution PWM_TOP = PWM_TOP_INIT; + // set up interrupt for delta-sigma modulation + // (moved to hwdef.c functions so it can be enabled/disabled based on ramp level) + //TIMSK |= (1<<TOIE1); // interrupt once for each timer 1 cycle + // set up e-switch SWITCH_PUE = (1 << SWITCH_PIN); // pull-up for e-switch SWITCH_PCMSK = (1 << SWITCH_PCINT); // enable pin change interrupt } + #define LAYOUT_DEFINED |