diff options
Diffstat (limited to '')
| -rw-r--r-- | hwdef-FW3A.h | 51 | ||||
| -rw-r--r-- | hwdef-fw3a.c | 71 | ||||
| -rw-r--r-- | hwdef-fw3a.h | 105 |
3 files changed, 176 insertions, 51 deletions
diff --git a/hwdef-FW3A.h b/hwdef-FW3A.h deleted file mode 100644 index f2b5c8d..0000000 --- a/hwdef-FW3A.h +++ /dev/null @@ -1,51 +0,0 @@ -// BLF/TLF FW3A driver layout -// Copyright (C) 2018-2023 Selene ToyKeeper -// SPDX-License-Identifier: GPL-3.0-or-later -#pragma once - -/* - * ---- - * Reset -|1 8|- VCC - * eswitch -|2 7|- optic nerve - * FET -|3 6|- 7x7135 - * GND -|4 5|- 1x7135 - * ---- - */ - -#define PWM_CHANNELS 3 - -#ifndef SWITCH_PIN -#define SWITCH_PIN PB3 // pin 2 -#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt -#endif - -#ifndef PWM1_PIN -#define PWM1_PIN PB0 // pin 5, 1x7135 PWM -#define PWM1_LVL OCR0A // OCR0A is the output compare register for PB0 -#endif -#ifndef PWM2_PIN -#define PWM2_PIN PB1 // pin 6, 7x7135 PWM -#define PWM2_LVL OCR0B // OCR0B is the output compare register for PB1 -#endif -#ifndef PWM3_PIN -#define PWM3_PIN PB4 // pin 3, FET PWM -#define PWM3_LVL OCR1B // OCR1B is the output compare register for PB4 -#endif - -#ifndef VISION_PIN -#define VISION_PIN PB2 // pin 7, optic nerve -//#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2 -//#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2 -#endif -#define ADC_PRSCL 0x07 // clk/128 - -// average drop across diode on this hardware -#ifndef VOLTAGE_FUDGE_FACTOR -#define VOLTAGE_FUDGE_FACTOR 5 // add 0.25V -#endif - -#define FAST 0xA3 // fast PWM both channels -#define PHASE 0xA1 // phase-correct PWM both channels - -#define LAYOUT_DEFINED - diff --git a/hwdef-fw3a.c b/hwdef-fw3a.c new file mode 100644 index 0000000..b20969d --- /dev/null +++ b/hwdef-fw3a.c @@ -0,0 +1,71 @@ +// BLF/TLF FW3A PWM helper functions +// Copyright (C) 2019-2023 Selene ToyKeeper +// SPDX-License-Identifier: GPL-3.0-or-later +#pragma once + +void set_level_zero(); + +void set_level_main(uint8_t level); +bool gradual_tick_main(uint8_t gt); + + +Channel channels[] = { + { // main LEDs + .set_level = set_level_main, + .gradual_tick = gradual_tick_main + }, +}; + + +void set_level_zero() { + CH1_PWM = 0; + CH2_PWM = 0; + #ifdef CH3_PIN + CH3_PWM = 0; + #endif +} + +// TODO: implement delta-sigma modulation for better low modes + +// single set of LEDs with 3 stacked power channels, FET+N+1 +// (or just use N+1 on the no-FET model or FET+1 model) +void set_level_main(uint8_t level) { + PWM_DATATYPE ch1_pwm = PWM_GET(pwm1_levels, level); + PWM_DATATYPE ch2_pwm = PWM_GET(pwm2_levels, level); + #ifdef CH3_PIN + PWM_DATATYPE ch3_pwm = PWM_GET(pwm3_levels, level); + #endif + + CH1_PWM = ch1_pwm; + CH2_PWM = ch2_pwm; + #ifdef CH3_PIN + CH3_PWM = ch3_pwm; + #endif +} + +bool gradual_tick_main(uint8_t gt) { + PWM_DATATYPE pwm1 = PWM_GET(pwm1_levels, gt); + PWM_DATATYPE pwm2 = PWM_GET(pwm2_levels, gt); + #ifdef CH3_PIN + PWM_DATATYPE pwm3 = PWM_GET(pwm3_levels, gt); + #endif + + GRADUAL_ADJUST_STACKED(pwm1, CH1_PWM, PWM_TOP_INIT); + #ifdef CH3_PIN + GRADUAL_ADJUST_STACKED(pwm2, CH2_PWM, PWM_TOP_INIT); + GRADUAL_ADJUST_SIMPLE (pwm3, CH3_PWM); + #else + GRADUAL_ADJUST_SIMPLE (pwm2, CH2_PWM); + #endif + + if ( (pwm1 == CH1_PWM) + && (pwm2 == CH2_PWM) + #ifdef CH3_PIN + && (pwm3 == CH3_PWM) + #endif + ) { + return true; // done + } + return false; // not done yet +} + diff --git a/hwdef-fw3a.h b/hwdef-fw3a.h new file mode 100644 index 0000000..519fb97 --- /dev/null +++ b/hwdef-fw3a.h @@ -0,0 +1,105 @@ +// BLF/TLF FW3A driver layout +// Copyright (C) 2018-2023 Selene ToyKeeper +// SPDX-License-Identifier: GPL-3.0-or-later +#pragma once + +/* + * ---- + * Reset -|1 8|- VCC + * eswitch -|2 7|- optic nerve + * FET -|3 6|- 7x7135 + * GND -|4 5|- 1x7135 + * ---- + */ + +#define ATTINY 85 +#include <avr/io.h> + +#define HWDEF_C_FILE hwdef-fw3a.c + +// channel modes +// * 0. FET+7+1 stacked +#define NUM_CHANNEL_MODES 1 +enum CHANNEL_MODES { + CM_MAIN = 0, +}; + +#define DEFAULT_CHANNEL_MODE CM_MAIN + +// right-most bit first, modes are in fedcba9876543210 order +#define CHANNEL_MODES_ENABLED 0b00000001 + + +#define PWM_CHANNELS 3 // old, remove this + +#define PWM_BITS 8 // attiny85 only supports up to 8 bits +#define PWM_GET PWM_GET8 +#define PWM_DATATYPE uint8_t +#define PWM_DATATYPE2 uint16_t +#define PWM1_DATATYPE uint8_t // 1x7135 ramp +#define PWM2_DATATYPE uint8_t // 7x7135 ramp +#define PWM3_DATATYPE uint8_t // DD FET ramp + +#define PWM_TOP_INIT 255 // highest value used in top half of ramp + +// 1x7135 channel +#define CH1_PIN PB0 // pin 5, 1x7135 PWM +#define CH1_PWM OCR0A // OCR0A is the output compare register for PB0 + +// 7x7135 channel +#define CH2_PIN PB1 // pin 6, 7x7135 PWM +#define CH2_PWM OCR0B // OCR0B is the output compare register for PB1 + +// DD FET channel +#define CH3_PIN PB4 // pin 3, FET PWM +#define CH3_PWM OCR1B // OCR1B is the output compare register for PB4 + +// e-switch +#ifndef SWITCH_PIN +#define SWITCH_PIN PB3 // pin 2 +#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt +#endif + +#ifndef VISION_PIN +#define VISION_PIN PB2 // pin 7, optic nerve +//#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2 +//#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2 +#endif +#define ADC_PRSCL 0x07 // clk/128 + +// average drop across diode on this hardware +#ifndef VOLTAGE_FUDGE_FACTOR +#define VOLTAGE_FUDGE_FACTOR 5 // add 0.25V +#endif + +#define FAST 0xA3 // fast PWM both channels +#define PHASE 0xA1 // phase-correct PWM both channels + + +inline void hwdef_setup() { + + // configure PWM channels + DDRB = (1 << CH1_PIN) + | (1 << CH2_PIN) + | (1 << CH3_PIN); + + // configure PWM channels + TCCR0B = 0x01; // pre-scaler for timer (1 => 1, 2 => 8, 3 => 64...) + TCCR0A = PHASE; + + // Second PWM counter is ... weird + TCCR1 = _BV (CS10); + GTCCR = _BV (COM1B1) | _BV (PWM1B); + OCR1C = PWM_TOP_INIT; // Set ceiling value to maximum + + // configure e-switch + PORTB = (1 << SWITCH_PIN); // e-switch is the only input + PCMSK = (1 << SWITCH_PIN); // pin change interrupt uses this pin + + // TODO: set up the vision pin + +} + + +#define LAYOUT_DEFINED + |