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-rw-r--r--tk-attiny.h35
1 files changed, 34 insertions, 1 deletions
diff --git a/tk-attiny.h b/tk-attiny.h
index 6390416..4058fea 100644
--- a/tk-attiny.h
+++ b/tk-attiny.h
@@ -36,7 +36,7 @@
#define F_CPU 8000000UL
#define EEPSIZE 128
#define V_REF REFS1
- #define BOGOMIPS 2000
+ #define BOGOMIPS (F_CPU/3200)
#else
Hey, you need to define ATTINY.
#endif
@@ -75,6 +75,39 @@
#endif // FET_7135_LAYOUT
+#ifdef TRIPLEDOWN_LAYOUT
+/*
+ * ----
+ * Reset -|1 8|- VCC
+ * OTC -|2 7|- Voltage ADC
+ * PWM (FET) -|3 6|- PWM (6x7135)
+ * GND -|4 5|- PWM (1x7135)
+ * ----
+ */
+
+#define STAR2_PIN PB0 // If this pin isn't used for ALT_PWM
+
+#define CAP_PIN PB3 // pin 2, OTC
+#define CAP_CHANNEL 0x03 // MUX 03 corresponds with PB3 (Star 4)
+#define CAP_DIDR ADC3D // Digital input disable bit corresponding with PB3
+
+#define PWM_PIN PB1 // pin 6, 6x7135 PWM
+#define PWM_LVL OCR0B // OCR0B is the output compare register for PB1
+#define ALT_PWM_PIN PB0 // pin 5, 1x7135 PWM
+#define ALT_PWM_LVL OCR0A // OCR0A is the output compare register for PB0
+#define FET_PWM_PIN PB4 // pin 3
+#define FET_PWM_LVL OCR1B // output compare register for PB4
+
+#define VOLTAGE_PIN PB2 // pin 7, voltage ADC
+#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2
+#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2
+#define ADC_PRSCL 0x06 // clk/64
+
+//#define TEMP_DIDR ADC4D
+#define TEMP_CHANNEL 0b00001111
+
+#endif // FET_7135_LAYOUT
+
#ifdef FERRERO_ROCHER_LAYOUT
/*
* ----