From 0df827391ced9bb0b7114248c78b696de4676b25 Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Sat, 28 Sep 2019 23:14:16 -0600
Subject: remapped D1S V2 pins to match new driver (and changed a bit about how
 ADC / DIDR definitions work, since this now uses DIDR1 instead of DIDR0)

---
 hwdef-BLF_GT.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'hwdef-BLF_GT.h')

diff --git a/hwdef-BLF_GT.h b/hwdef-BLF_GT.h
index 01dbdbd..dd8d80a 100644
--- a/hwdef-BLF_GT.h
+++ b/hwdef-BLF_GT.h
@@ -34,7 +34,9 @@
 #ifndef VOLTAGE_PIN
 #define VOLTAGE_PIN PB2     // pin 7, voltage ADC
 #define VOLTAGE_CHANNEL 0x01 // MUX 01 corresponds with PB2
-#define VOLTAGE_ADC_DIDR ADC1D  // Digital input disable bit corresponding with PB2
+#define VOLTAGE_ADC ADC1D  // Digital input disable bit corresponding with PB2
+// inherited from tk-attiny.h
+//#define VOLTAGE_ADC_DIDR DIDR0  // DIDR for ADC1
 // 1.1V reference, left-adjust, ADC1/PB2
 //#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | (1 << ADLAR) | VOLTAGE_CHANNEL)
 // 1.1V reference, no left-adjust, ADC1/PB2
-- 
cgit v1.2.3


From 1ab6cd428c3b43a80ffac01f29ca0c27a438e3b1 Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Mon, 25 Nov 2019 18:41:24 -0700
Subject: calibrated Noctigon K1, changed voltage divider calibration values to
 10-bit (was 8-bit before)

---
 hwdef-BLF_GT.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'hwdef-BLF_GT.h')

diff --git a/hwdef-BLF_GT.h b/hwdef-BLF_GT.h
index dd8d80a..8ad99c7 100644
--- a/hwdef-BLF_GT.h
+++ b/hwdef-BLF_GT.h
@@ -46,10 +46,10 @@
 
 // Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line)
 #ifndef ADC_44
-#define ADC_44 184
+#define ADC_44 (184*4)
 #endif
 #ifndef ADC_22
-#define ADC_22 92
+#define ADC_22 (92*4)
 #endif
 
 #define TEMP_CHANNEL 0b00001111
-- 
cgit v1.2.3


From 9c0d1832464e4ee7ee8c4c63092ac4337347483b Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Wed, 29 Jan 2020 05:08:14 -0700
Subject: rewrote ADC code to use a continuous lowpass system on all
 measurements, to eliminate noise and maybe increase precision (thermal code
 still needs to be rewritten though)

---
 hwdef-BLF_GT.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'hwdef-BLF_GT.h')

diff --git a/hwdef-BLF_GT.h b/hwdef-BLF_GT.h
index 01dbdbd..f0ac103 100644
--- a/hwdef-BLF_GT.h
+++ b/hwdef-BLF_GT.h
@@ -40,7 +40,7 @@
 // 1.1V reference, no left-adjust, ADC1/PB2
 #define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL)
 #endif
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line)
 #ifndef ADC_44
-- 
cgit v1.2.3


From f61beefe38f5118dc816d5ba28d7e41001cfe703 Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Thu, 30 Jan 2020 01:18:56 -0700
Subject: switched to a pseudo-rolling-average method to reduce noise, set
 prescaler back to 64

---
 hwdef-BLF_GT.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'hwdef-BLF_GT.h')

diff --git a/hwdef-BLF_GT.h b/hwdef-BLF_GT.h
index f0ac103..01dbdbd 100644
--- a/hwdef-BLF_GT.h
+++ b/hwdef-BLF_GT.h
@@ -40,7 +40,7 @@
 // 1.1V reference, no left-adjust, ADC1/PB2
 #define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL)
 #endif
-#define ADC_PRSCL   0x07    // clk/128
+#define ADC_PRSCL   0x06    // clk/64
 
 // Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line)
 #ifndef ADC_44
-- 
cgit v1.2.3


From 51aae811654a3b73fa10ab449e22a11c858aa2d1 Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Fri, 13 Mar 2020 18:04:43 -0600
Subject: went back to slower clk/128 ADC timing

---
 hwdef-BLF_GT.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'hwdef-BLF_GT.h')

diff --git a/hwdef-BLF_GT.h b/hwdef-BLF_GT.h
index 01dbdbd..f0ac103 100644
--- a/hwdef-BLF_GT.h
+++ b/hwdef-BLF_GT.h
@@ -40,7 +40,7 @@
 // 1.1V reference, no left-adjust, ADC1/PB2
 #define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL)
 #endif
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line)
 #ifndef ADC_44
-- 
cgit v1.2.3


From 635d013abd690315e4e57caf1f47f1f06b6eba58 Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Wed, 29 Apr 2020 01:40:25 -0600
Subject: removed unused TEMP_CHANNEL thing from FSM-related code

---
 hwdef-BLF_GT.h | 2 --
 1 file changed, 2 deletions(-)

(limited to 'hwdef-BLF_GT.h')

diff --git a/hwdef-BLF_GT.h b/hwdef-BLF_GT.h
index 99adc8f..51b391d 100644
--- a/hwdef-BLF_GT.h
+++ b/hwdef-BLF_GT.h
@@ -52,8 +52,6 @@
 #define ADC_22 (92*4)
 #endif
 
-#define TEMP_CHANNEL 0b00001111
-
 #define FAST 0xA3           // fast PWM both channels
 #define PHASE 0xA1          // phase-correct PWM both channels
 
-- 
cgit v1.2.3