From 2e192ce780b0a70f11142eb7c33880b0529df6eb Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Sat, 28 Oct 2023 07:34:07 -0600
Subject: converted emisar-d18 to new API (it's mostly the same as FW3A)

---
 hwdef-Emisar_D18.h | 49 -------------------------------------------------
 1 file changed, 49 deletions(-)
 delete mode 100644 hwdef-Emisar_D18.h

(limited to 'hwdef-Emisar_D18.h')

diff --git a/hwdef-Emisar_D18.h b/hwdef-Emisar_D18.h
deleted file mode 100644
index b9f5b2e..0000000
--- a/hwdef-Emisar_D18.h
+++ /dev/null
@@ -1,49 +0,0 @@
-// Emisar D18 (FET+13+1) driver layout
-// Copyright (C) 2019-2023 Selene ToyKeeper
-// SPDX-License-Identifier: GPL-3.0-or-later
-#pragma once
-
-/*
- *           ----
- *   Reset -|1  8|- VCC
- * eswitch -|2  7|- aux LED?
- *     FET -|3  6|- 13x7135
- *     GND -|4  5|-  1x7135
- *           ----
- */
-
-#define PWM_CHANNELS 3
-
-#ifndef SWITCH_PIN
-#define SWITCH_PIN   PB3    // pin 2
-#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt
-#endif
-
-#ifndef PWM1_PIN
-#define PWM1_PIN PB0        // pin 5, 1x7135 PWM
-#define PWM1_LVL OCR0A      // OCR0A is the output compare register for PB0
-#endif
-#ifndef PWM2_PIN
-#define PWM2_PIN PB1        // pin 6, 7x7135 PWM
-#define PWM2_LVL OCR0B      // OCR0B is the output compare register for PB1
-#endif
-#ifndef PWM3_PIN
-#define PWM3_PIN PB4        // pin 3, FET PWM
-#define PWM3_LVL OCR1B      // OCR1B is the output compare register for PB4
-#endif
-
-#ifndef AUXLED_PIN
-#define AUXLED_PIN PB2      // pin 7
-#endif
-#define ADC_PRSCL   0x07    // clk/128
-
-// average drop across diode on this hardware
-#ifndef VOLTAGE_FUDGE_FACTOR
-#define VOLTAGE_FUDGE_FACTOR 5  // add 0.25V
-#endif
-
-#define FAST 0xA3           // fast PWM both channels
-#define PHASE 0xA1          // phase-correct PWM both channels
-
-#define LAYOUT_DEFINED
-
-- 
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