From 9c0d1832464e4ee7ee8c4c63092ac4337347483b Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Wed, 29 Jan 2020 05:08:14 -0700
Subject: rewrote ADC code to use a continuous lowpass system on all
 measurements, to eliminate noise and maybe increase precision (thermal code
 still needs to be rewritten though)

---
 hwdef-Emisar_D4Sv2.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'hwdef-Emisar_D4Sv2.h')

diff --git a/hwdef-Emisar_D4Sv2.h b/hwdef-Emisar_D4Sv2.h
index da3a0ca..7c3fe86 100644
--- a/hwdef-Emisar_D4Sv2.h
+++ b/hwdef-Emisar_D4Sv2.h
@@ -52,7 +52,7 @@
 #define PWM3_LVL OCR1B      // OCR1B is the output compare register for PB1
 
 
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // average drop across diode on this hardware
 #ifndef VOLTAGE_FUDGE_FACTOR
-- 
cgit v1.2.3


From f61beefe38f5118dc816d5ba28d7e41001cfe703 Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Thu, 30 Jan 2020 01:18:56 -0700
Subject: switched to a pseudo-rolling-average method to reduce noise, set
 prescaler back to 64

---
 hwdef-Emisar_D4Sv2.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'hwdef-Emisar_D4Sv2.h')

diff --git a/hwdef-Emisar_D4Sv2.h b/hwdef-Emisar_D4Sv2.h
index 7c3fe86..da3a0ca 100644
--- a/hwdef-Emisar_D4Sv2.h
+++ b/hwdef-Emisar_D4Sv2.h
@@ -52,7 +52,7 @@
 #define PWM3_LVL OCR1B      // OCR1B is the output compare register for PB1
 
 
-#define ADC_PRSCL   0x07    // clk/128
+#define ADC_PRSCL   0x06    // clk/64
 
 // average drop across diode on this hardware
 #ifndef VOLTAGE_FUDGE_FACTOR
-- 
cgit v1.2.3


From 51aae811654a3b73fa10ab449e22a11c858aa2d1 Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Fri, 13 Mar 2020 18:04:43 -0600
Subject: went back to slower clk/128 ADC timing

---
 hwdef-Emisar_D4Sv2.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'hwdef-Emisar_D4Sv2.h')

diff --git a/hwdef-Emisar_D4Sv2.h b/hwdef-Emisar_D4Sv2.h
index da3a0ca..7c3fe86 100644
--- a/hwdef-Emisar_D4Sv2.h
+++ b/hwdef-Emisar_D4Sv2.h
@@ -52,7 +52,7 @@
 #define PWM3_LVL OCR1B      // OCR1B is the output compare register for PB1
 
 
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // average drop across diode on this hardware
 #ifndef VOLTAGE_FUDGE_FACTOR
-- 
cgit v1.2.3