From 51aae811654a3b73fa10ab449e22a11c858aa2d1 Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Fri, 13 Mar 2020 18:04:43 -0600
Subject: went back to slower clk/128 ADC timing

---
 hwdef-Emisar_D4v2.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'hwdef-Emisar_D4v2.h')

diff --git a/hwdef-Emisar_D4v2.h b/hwdef-Emisar_D4v2.h
index addf429..60f3fae 100644
--- a/hwdef-Emisar_D4v2.h
+++ b/hwdef-Emisar_D4v2.h
@@ -48,7 +48,7 @@
 #define PWM2_LVL OCR1B      // OCR1B is the output compare register for PB1
 
 
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // average drop across diode on this hardware
 #ifndef VOLTAGE_FUDGE_FACTOR
-- 
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