From 51aae811654a3b73fa10ab449e22a11c858aa2d1 Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Fri, 13 Mar 2020 18:04:43 -0600
Subject: went back to slower clk/128 ADC timing

---
 hwdef-FW3A.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'hwdef-FW3A.h')

diff --git a/hwdef-FW3A.h b/hwdef-FW3A.h
index 0b94635..a223b08 100644
--- a/hwdef-FW3A.h
+++ b/hwdef-FW3A.h
@@ -35,7 +35,7 @@
 //#define ADC_CHANNEL 0x01    // MUX 01 corresponds with PB2
 //#define ADC_DIDR    ADC1D   // Digital input disable bit corresponding with PB2
 #endif
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // average drop across diode on this hardware
 #ifndef VOLTAGE_FUDGE_FACTOR
-- 
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