From 51aae811654a3b73fa10ab449e22a11c858aa2d1 Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Fri, 13 Mar 2020 18:04:43 -0600
Subject: went back to slower clk/128 ADC timing

---
 hwdef-Mateminco_MF01S.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'hwdef-Mateminco_MF01S.h')

diff --git a/hwdef-Mateminco_MF01S.h b/hwdef-Mateminco_MF01S.h
index ab1c5bf..b89408f 100644
--- a/hwdef-Mateminco_MF01S.h
+++ b/hwdef-Mateminco_MF01S.h
@@ -40,7 +40,7 @@
 // 1.1V reference, no left-adjust, ADC1/PB2
 #define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL)
 #endif
-#define ADC_PRSCL   0x06    // clk/64
+#define ADC_PRSCL   0x07    // clk/128
 
 // Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line)
 #ifndef ADC_44
-- 
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