From bcaa751aa1b29cb3b4c76df2075feb1941d043fe Mon Sep 17 00:00:00 2001
From: Selene ToyKeeper
Date: Thu, 3 Aug 2023 19:15:34 -0600
Subject: converted all K9.3 builds and D4Sv2-tintramp-fet (now emisar-2ch-fet)
 to multi-channel, and removed old K9.3 builds which aren't relevant any more,
 and old D4Sv2-tintramp builds

---
 hwdef-emisar-2ch.h | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

(limited to 'hwdef-emisar-2ch.h')

diff --git a/hwdef-emisar-2ch.h b/hwdef-emisar-2ch.h
index 32cbc3b..6d43a24 100644
--- a/hwdef-emisar-2ch.h
+++ b/hwdef-emisar-2ch.h
@@ -26,6 +26,9 @@
  *  19    PB0   (none)
  *  20    PA7   e-switch (PCINT7)
  *      ADC12   thermal sensor
+ *
+ * Both sets of LEDs use one pin to turn the Opamp on/off,
+ * and one pin to control the Opamp power level.
  */
 
 #define ATTINY 1634
@@ -62,7 +65,7 @@ enum channel_modes_e {
 #define USE_CALC_2CH_BLEND
 
 
-#define PWM_CHANNELS 1  // old, remove this
+#define PWM_CHANNELS 2  // old, remove this
 
 #define PWM_BITS      16     // 0 to 16383 at variable Hz, not 0 to 255 at 16 kHz
 #define PWM_GET       PWM_GET16
@@ -77,18 +80,21 @@ enum channel_modes_e {
 #define PWM_TOP_INIT  511    // highest value used in top half of ramp
 #define PWM_CNT       TCNT1  // for dynamic PWM, reset phase
 
+// main LEDs, linear
 #define CH1_PIN  PB3            // pin 16, Opamp reference
 #define CH1_PWM  OCR1A          // OCR1A is the output compare register for PB3
 #define CH1_ENABLE_PIN   PA0    // pin 7, Opamp power
 #define CH1_ENABLE_PORT  PORTA  // control port for PA0
 
+// 2nd LEDs, linear
 #define CH2_PIN  PA6            // pin 1, 2nd LED Opamp reference
 #define CH2_PWM  OCR1B          // OCR1B is the output compare register for PA6
 #define CH2_ENABLE_PIN   PA1    // pin 6, Opamp power
 #define CH2_ENABLE_PORT  PORTA  // control port for PA1
 
+// main LEDs, DD FET
 //#define CH3_PIN  PC0            // pin 15, DD FET PWM
-//#define CH3_LVL  OCR0A          // OCR0A is the output compare register for PC0
+//#define CH3_PWM  OCR0A          // OCR0A is the output compare register for PC0
 
 // e-switch
 #ifndef SWITCH_PIN
@@ -175,19 +181,21 @@ inline void hwdef_setup() {
             ;
 
     // unused on this driver
+    #if 0
     // FET PWM (8-bit; this channel can't do 10-bit)
     // WGM0[2:0]: 0,0,1: PWM, Phase Correct, 8-bit (DS table 11-8)
     // CS0[2:0]:  0,0,1: clk/1 (No prescaling) (DS table 11-9)
     // COM0A[1:0]:  1,0: PWM OC0A in the normal direction (DS table 11-4)
     // COM0B[1:0]:  1,0: PWM OC0B in the normal direction (DS table 11-7)
-    //TCCR0A  = (0<<WGM01)  | (1<<WGM00)   // 8-bit (TOP=0xFF) (DS table 11-8)
-    //        | (1<<COM0A1) | (0<<COM0A0)  // PWM 0A in normal direction (DS table 11-4)
-    //        //| (1<<COM0B1) | (0<<COM0B0)  // PWM 0B in normal direction (DS table 11-7)
-    //        ;
-    //TCCR0B  = (0<<CS02)   | (0<<CS01) | (1<<CS00)  // clk/1 (no prescaling) (DS table 11-9)
-    //        | (0<<WGM02)  // phase-correct PWM (DS table 11-8)
-    //        ;
-    //CH3_LVL = 0;  // ensure this channel is off, if it exists
+    TCCR0A  = (0<<WGM01)  | (1<<WGM00)   // 8-bit (TOP=0xFF) (DS table 11-8)
+            | (1<<COM0A1) | (0<<COM0A0)  // PWM 0A in normal direction (DS table 11-4)
+            //| (1<<COM0B1) | (0<<COM0B0)  // PWM 0B in normal direction (DS table 11-7)
+            ;
+    TCCR0B  = (0<<CS02)   | (0<<CS01) | (1<<CS00)  // clk/1 (no prescaling) (DS table 11-9)
+            | (0<<WGM02)  // phase-correct PWM (DS table 11-8)
+            ;
+    CH3_PWM = 0;  // ensure this channel is off, if it exists
+    #endif
 
     // set PWM resolution
     PWM_TOP = PWM_TOP_INIT;
-- 
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