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| author | Uri Shaked | 2021-08-07 18:31:03 +0300 |
|---|---|---|
| committer | Uri Shaked | 2021-08-07 18:31:03 +0300 |
| commit | fad050603cf3fa18cacb79ec4b09665d2aba48b5 (patch) | |
| tree | bfa455f0c5b50da1a0a425abc20c8038938c059b | |
| parent | 0.16.4 (diff) | |
| download | avr8js-fad050603cf3fa18cacb79ec4b09665d2aba48b5.tar.gz avr8js-fad050603cf3fa18cacb79ec4b09665d2aba48b5.tar.bz2 avr8js-fad050603cf3fa18cacb79ec4b09665d2aba48b5.zip | |
style(spi): remove redundant whitespace from comments
Diffstat (limited to '')
| -rw-r--r-- | src/peripherals/spi.ts | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/peripherals/spi.ts b/src/peripherals/spi.ts index 80167b0..9707307 100644 --- a/src/peripherals/spi.ts +++ b/src/peripherals/spi.ts @@ -10,10 +10,10 @@ export interface SPIConfig { } // Register bits: -const SPCR_SPIE = 0x80; // SPI Interrupt Enable +const SPCR_SPIE = 0x80; // SPI Interrupt Enable const SPCR_SPE = 0x40; // SPI Enable const SPCR_DORD = 0x20; // Data Order -const SPCR_MSTR = 0x10; // Master/Slave Select +const SPCR_MSTR = 0x10; // Master/Slave Select const SPCR_CPOL = 0x8; // Clock Polarity const SPCR_CPHA = 0x4; // Clock Phase const SPCR_SPR1 = 0x2; // SPI Clock Rate Select 1 |