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authorUri Shaked2020-05-10 09:01:53 +0300
committerUri Shaked2020-05-10 09:01:53 +0300
commiteed745eaca8af2a5f8a7a4e40e84828b8c155dc8 (patch)
tree714f6766006dea0d216996939207965eace1b8b6 /src/peripherals/gpio.spec.ts
parentrefactor(demo): use pinState() method (diff)
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feat(gpio): add setPin() function
close #26
Diffstat (limited to 'src/peripherals/gpio.spec.ts')
-rw-r--r--src/peripherals/gpio.spec.ts23
1 files changed, 23 insertions, 0 deletions
diff --git a/src/peripherals/gpio.spec.ts b/src/peripherals/gpio.spec.ts
index f3b1a0f..1dfaf7d 100644
--- a/src/peripherals/gpio.spec.ts
+++ b/src/peripherals/gpio.spec.ts
@@ -93,4 +93,27 @@ describe('GPIO', () => {
expect(listener).toHaveBeenCalled();
});
});
+
+ describe('setPin', () => {
+ it('should set the value of the given pin', () => {
+ const cpu = new CPU(new Uint16Array(1024));
+ const port = new AVRIOPort(cpu, portBConfig);
+ cpu.writeData(0x24, 0); // DDRB <- 0
+ port.setPin(4, true);
+ expect(cpu.data[0x23]).toEqual(0x10);
+ port.setPin(4, false);
+ expect(cpu.data[0x23]).toEqual(0x0);
+ });
+
+ it('should only update PIN register when pin in Input mode', () => {
+ const cpu = new CPU(new Uint16Array(1024));
+ const port = new AVRIOPort(cpu, portBConfig);
+ cpu.writeData(0x24, 0x10); // DDRB <- 0x10
+ cpu.writeData(0x25, 0x0); // PORTB <- 0x0
+ port.setPin(4, true);
+ expect(cpu.data[0x23]).toEqual(0x0);
+ cpu.writeData(0x24, 0x0); // DDRB <- 0x0
+ expect(cpu.data[0x23]).toEqual(0x10);
+ });
+ });
});