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authorUri Shaked2020-12-09 15:46:53 +0200
committerUri Shaked2020-12-09 15:49:41 +0200
commit9c1288f18889ae3bd10869a9f6ebc53defa3024b (patch)
tree1857fe48d3e2d32a39cfe810a0dfdd7d96526b3a /src/peripherals/spi.spec.ts
parentrefactor: central interrupt handling #38 (diff)
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perf!: centeral timekeeping
This should improve performance, especially when running simulations with multiple peripherals. For instance, the demo project now runs at ~322%, up from ~185% in AVR8js 0.13.1. BREAKING CHANGE: `tick()` methods were removed from individual peripherals. You now need to call `cpu.tick()` instead.
Diffstat (limited to '')
-rw-r--r--src/peripherals/spi.spec.ts11
1 files changed, 3 insertions, 8 deletions
diff --git a/src/peripherals/spi.spec.ts b/src/peripherals/spi.spec.ts
index 8e11b94..635e657 100644
--- a/src/peripherals/spi.spec.ts
+++ b/src/peripherals/spi.spec.ts
@@ -160,7 +160,7 @@ describe('SPI', () => {
return 0x5b; // we copy this byte to
};
- const runner = new TestProgramRunner(cpu, spi);
+ const runner = new TestProgramRunner(cpu);
runner.runToBreak();
// 16 cycles per clock * 8 bits = 128
@@ -172,11 +172,10 @@ describe('SPI', () => {
it('should set the WCOL bit in SPSR if writing to SPDR while SPI is already transmitting', () => {
const cpu = new CPU(new Uint16Array(1024));
- const spi = new AVRSPI(cpu, spiConfig, FREQ_16MHZ);
+ new AVRSPI(cpu, spiConfig, FREQ_16MHZ);
cpu.writeData(SPCR, SPE | MSTR);
cpu.writeData(SPDR, 0x50);
- spi.tick();
cpu.tick();
expect(cpu.readData(SPSR) & WCOL).toEqual(0);
@@ -186,7 +185,7 @@ describe('SPI', () => {
it('should clear the SPIF bit and fire an interrupt when SPI transfer completes', () => {
const cpu = new CPU(new Uint16Array(1024));
- const spi = new AVRSPI(cpu, spiConfig, FREQ_16MHZ);
+ new AVRSPI(cpu, spiConfig, FREQ_16MHZ);
cpu.writeData(SPCR, SPE | SPIE | MSTR);
cpu.writeData(SPDR, 0x50);
@@ -194,13 +193,11 @@ describe('SPI', () => {
// At this point, write shouldn't be complete yet
cpu.cycles += 10;
- spi.tick();
cpu.tick();
expect(cpu.pc).toEqual(0);
// 100 cycles later, it should (8 bits * 8 cycles per bit = 64).
cpu.cycles += 100;
- spi.tick();
cpu.tick();
expect(cpu.data[SPSR] & SPIF).toEqual(0);
expect(cpu.pc).toEqual(0x22); // SPI Ready interrupt
@@ -215,12 +212,10 @@ describe('SPI', () => {
cpu.writeData(SPDR, 0x8f);
cpu.cycles = 10;
- spi.tick();
cpu.tick();
expect(cpu.readData(SPDR)).toEqual(0);
cpu.cycles = 32; // 4 cycles per bit * 8 bits = 32
- spi.tick();
cpu.tick();
expect(cpu.readData(SPDR)).toEqual(0x88);
});