aboutsummaryrefslogtreecommitdiff
path: root/src/peripherals/timer.ts
diff options
context:
space:
mode:
authorUri Shaked2020-09-02 23:23:21 +0300
committerUri Shaked2020-09-02 23:23:21 +0300
commit673cbaf83872e8a81370f215c4644185eaf1f783 (patch)
tree11552483c8cb84f03f0322cab07ac51959bac15b /src/peripherals/timer.ts
parent0.11.1 (diff)
downloadavr8js-673cbaf83872e8a81370f215c4644185eaf1f783.tar.gz
avr8js-673cbaf83872e8a81370f215c4644185eaf1f783.tar.bz2
avr8js-673cbaf83872e8a81370f215c4644185eaf1f783.zip
perf(timer): improve timer speed
cache the value of the clock divider
Diffstat (limited to '')
-rw-r--r--src/peripherals/timer.ts7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/peripherals/timer.ts b/src/peripherals/timer.ts
index 315d725..dc1302a 100644
--- a/src/peripherals/timer.ts
+++ b/src/peripherals/timer.ts
@@ -231,6 +231,7 @@ export class AVRTimer {
private compB: CompBitsValue;
private tcntUpdated = false;
private countingUp = true;
+ private divider = 0;
// This is the temporary register used to access 16-bit registers (section 16.3 of the datasheet)
private highByteTemp: u8 = 0;
@@ -283,12 +284,14 @@ export class AVRTimer {
cpu.writeHooks[config.TCCRB] = (value) => {
this.cpu.data[config.TCCRB] = value;
this.tcntUpdated = true;
+ this.divider = this.config.dividers[this.CS];
this.updateWGMConfig();
return true;
};
}
reset() {
+ this.divider = 0;
this.lastCycle = 0;
this.ocrA = 0;
this.ocrB = 0;
@@ -342,8 +345,8 @@ export class AVRTimer {
}
tick() {
- const divider = this.config.dividers[this.CS];
- const delta = this.cpu.cycles - this.lastCycle;
+ const { divider, lastCycle } = this;
+ const delta = this.cpu.cycles - lastCycle;
if (divider && delta >= divider) {
const counterDelta = Math.floor(delta / divider);
this.lastCycle += counterDelta * divider;