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authorUri Shaked2020-04-27 21:50:22 +0300
committerUri Shaked2020-04-27 21:50:22 +0300
commit101ddbe191649cdf1eb7b8f0af613d31bd0d989c (patch)
tree4833f1600336ea42d72edf104f815c066bcd0488 /src/peripherals/timer.ts
parentfix(benchmark): update to work with latest code (diff)
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fix(timer): Timer value should not increment on the same cycle as TCNTn write
close #36
Diffstat (limited to 'src/peripherals/timer.ts')
-rw-r--r--src/peripherals/timer.ts10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/peripherals/timer.ts b/src/peripherals/timer.ts
index 6e805ee..ac344ef 100644
--- a/src/peripherals/timer.ts
+++ b/src/peripherals/timer.ts
@@ -191,11 +191,13 @@ export class AVRTimer {
private ocrB: u16 = 0;
private timerMode: TimerMode;
private topValue: TimerTopValue;
+ private tcntUpdated = false;
constructor(private cpu: CPU, private config: AVRTimerConfig) {
this.updateWGMConfig();
this.registerHook(config.TCNT, (value: u16) => {
this.TCNT = value;
+ this.tcntUpdated = true;
this.timerUpdated(value);
return true;
});
@@ -306,8 +308,11 @@ export class AVRTimer {
this.lastCycle += counterDelta * divider;
const val = this.TCNT;
const newVal = (val + counterDelta) % (this.TOP + 1);
- this.TCNT = newVal;
- this.timerUpdated(newVal);
+ // A CPU write overrides (has priority over) all counter clear or count operations.
+ if (!this.tcntUpdated) {
+ this.TCNT = newVal;
+ this.timerUpdated(newVal);
+ }
const { timerMode } = this;
if (
(timerMode === TimerMode.Normal ||
@@ -319,6 +324,7 @@ export class AVRTimer {
this.TIFR |= TOV;
}
}
+ this.tcntUpdated = false;
if (this.cpu.interruptsEnabled) {
if (this.TIFR & TOV && this.TIMSK & TOIE) {
avrInterrupt(this.cpu, this.config.ovfInterrupt);