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| author | Uri Shaked | 2020-07-09 16:16:42 +0300 |
|---|---|---|
| committer | Uri Shaked | 2020-07-09 16:16:42 +0300 |
| commit | 5a8330c20db9ef1ee7fa555e40c16a58c81c860d (patch) | |
| tree | 29d6d4954320215d56d14432541a86a80f3cc1e0 /src/peripherals/usart.ts | |
| parent | fix(usart): TXC interrupt triggered incorrectly (diff) | |
| download | avr8js-5a8330c20db9ef1ee7fa555e40c16a58c81c860d.tar.gz avr8js-5a8330c20db9ef1ee7fa555e40c16a58c81c860d.tar.bz2 avr8js-5a8330c20db9ef1ee7fa555e40c16a58c81c860d.zip | |
fix(usart): bitsPerChar looking at the wrong register
close #52
Diffstat (limited to '')
| -rw-r--r-- | src/peripherals/usart.ts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/peripherals/usart.ts b/src/peripherals/usart.ts index eb6171e..16d86f8 100644 --- a/src/peripherals/usart.ts +++ b/src/peripherals/usart.ts @@ -115,7 +115,7 @@ export class AVRUSART { get bitsPerChar() { const ucsz = - ((this.cpu.data[this.config.UCSRA] & (UCSRC_UCSZ1 | UCSRC_UCSZ0)) >> 1) | + ((this.cpu.data[this.config.UCSRC] & (UCSRC_UCSZ1 | UCSRC_UCSZ0)) >> 1) | (this.cpu.data[this.config.UCSRB] & UCSRB_UCSZ2); switch (ucsz) { case 0: |