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authorUri Shaked2019-11-30 20:05:43 +0200
committerUri Shaked2019-11-30 20:05:43 +0200
commit620b1f5872957518d758a6e0ca055d038bbfbeda (patch)
tree11f3b97aa38daba7d5a0af7629fca37aa5bc3770 /src/timer.spec.ts
parentfeat: Output Compare for Timers (diff)
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fix: Wrong prescaler for Timer2
fix #5
Diffstat (limited to 'src/timer.spec.ts')
-rw-r--r--src/timer.spec.ts15
1 files changed, 14 insertions, 1 deletions
diff --git a/src/timer.spec.ts b/src/timer.spec.ts
index dd45cee..4d631a7 100644
--- a/src/timer.spec.ts
+++ b/src/timer.spec.ts
@@ -1,5 +1,5 @@
import { CPU } from './cpu';
-import { AVRTimer, timer0Config } from './timer';
+import { AVRTimer, timer0Config, timer2Config } from './timer';
describe('timer', () => {
let cpu: CPU;
@@ -188,4 +188,17 @@ describe('timer', () => {
expect(cpu.pc).toEqual(0x1e);
expect(cpu.cycles).toEqual(3);
});
+
+ it('timer2 should count every 256 ticks when prescaler is 6 (issue #5)', () => {
+ const timer = new AVRTimer(cpu, timer2Config);
+ cpu.data[0xb1] = 0x6; // TCCR1B.CS <- 6
+
+ cpu.cycles = 511;
+ timer.tick();
+ expect(cpu.data[0xb2]).toEqual(1); // TCNT2 should be 2
+
+ cpu.cycles = 512;
+ timer.tick();
+ expect(cpu.data[0xb2]).toEqual(2); // TCNT2 should be 2
+ });
});