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authorUri Shaked2020-02-03 22:34:30 +0200
committerUri Shaked2020-02-03 22:34:30 +0200
commit13a112968c5527b10b974489d3a2ec19c98736d9 (patch)
tree1c0d9819541d4d3e43846c1971ce3418581e763e /src/twi.spec.ts
parenttest(twi): add master TWI receive test #10 (diff)
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feat(twi): proper interrupt support #10
Diffstat (limited to 'src/twi.spec.ts')
-rw-r--r--src/twi.spec.ts11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/twi.spec.ts b/src/twi.spec.ts
index de7ceb8..369f22a 100644
--- a/src/twi.spec.ts
+++ b/src/twi.spec.ts
@@ -46,6 +46,17 @@ describe('TWI', () => {
expect(twi.sclFrequency).toEqual(400000);
});
+ it('should trigger data an interrupt if TWINT is set', () => {
+ const cpu = new CPU(new Uint16Array(1024));
+ const twi = new AVRTWI(cpu, twiConfig, FREQ_16MHZ);
+ cpu.writeData(0xbc, 0x81); // TWCR <- TWINT | TWIE
+ cpu.data[95] = 0x80; // SREG: I-------
+ twi.tick();
+ expect(cpu.pc).toEqual(0x30); // 2-wire Serial Interface Vector
+ expect(cpu.cycles).toEqual(2);
+ expect(cpu.data[0xbc] & 0x80).toEqual(0); // UCSR0A should clear TWINT
+ });
+
describe('Master mode', () => {
it('should call the startEvent handler when TWSTA bit is written 1', () => {
const cpu = new CPU(new Uint16Array(1024));