diff options
| author | Uri Shaked | 2019-12-07 22:18:00 +0200 |
|---|---|---|
| committer | Uri Shaked | 2019-12-07 22:18:00 +0200 |
| commit | 07ddaa7d22f31de5d5c3b9c6d4626c59cf25a244 (patch) | |
| tree | 12a64bfbc4ea18997923f14b44725cb0e118c949 /src/usart.spec.ts | |
| parent | feat: publish both CJS and ESM to npm (diff) | |
| download | avr8js-07ddaa7d22f31de5d5c3b9c6d4626c59cf25a244.tar.gz avr8js-07ddaa7d22f31de5d5c3b9c6d4626c59cf25a244.tar.bz2 avr8js-07ddaa7d22f31de5d5c3b9c6d4626c59cf25a244.zip | |
refactor: tslint → eslint
Diffstat (limited to 'src/usart.spec.ts')
| -rw-r--r-- | src/usart.spec.ts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/usart.spec.ts b/src/usart.spec.ts index dadfc78..222017c 100644 --- a/src/usart.spec.ts +++ b/src/usart.spec.ts @@ -69,7 +69,7 @@ describe('USART', () => { it('should set UDRE and TXC flags after UDR0', () => { const cpu = new CPU(new Uint16Array(1024)); - const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ); + new AVRUSART(cpu, usart0Config, FREQ_16MHZ); cpu.writeData(0xc1, 0x8); // UCSR0B <- TXEN cpu.writeData(0xc0, 0); // UCSR0A <- 0 cpu.writeData(0xc6, 0x61); // UDR0 |