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authorUri Shaked2019-12-07 13:08:46 +0200
committerUri Shaked2019-12-07 13:08:46 +0200
commit92898c67a4da42992a8115ffa7b12781e49f2eae (patch)
tree00e94786829b3c2cef833e94b45efb393be06b6d /src/usart.ts
parentchore: update package-lock.json (diff)
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feat(usart): add onLineTransmit callback
Diffstat (limited to '')
-rw-r--r--src/usart.ts13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/usart.ts b/src/usart.ts
index da5cee0..8d5691c 100644
--- a/src/usart.ts
+++ b/src/usart.ts
@@ -28,6 +28,7 @@ export const usart0Config: USARTConfig = {
};
export type USARTTransmitCallback = (value: u8) => void;
+export type USARTLineTransmitCallback = (value: string) => void;
// Register bits
const UCSRA_RXC = 0x80; // USART Receive Complete
@@ -57,6 +58,9 @@ const UCSRC_UCPOL = 0x1; // Clock Polarity
export class AVRUSART {
public onByteTransmit: USARTTransmitCallback | null = null;
+ public onLineTransmit: USARTLineTransmitCallback | null = null;
+
+ private lineBuffer: string = '';
constructor(private cpu: CPU, private config: USARTConfig, private freqMHz: number) {
this.cpu.writeHooks[config.UCSRA] = (value) => {
@@ -73,6 +77,15 @@ export class AVRUSART {
if (this.onByteTransmit) {
this.onByteTransmit(value);
}
+ if (this.onLineTransmit) {
+ const ch = String.fromCharCode(value);
+ if (ch === '\n') {
+ this.onLineTransmit(this.lineBuffer);
+ this.lineBuffer = '';
+ } else {
+ this.lineBuffer += ch;
+ }
+ }
this.cpu.data[config.UCSRA] |= UCSRA_UDRE | UCSRA_TXC;
};
}