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| author | Uri Shaked | 2020-08-22 16:57:41 +0300 |
|---|---|---|
| committer | Uri Shaked | 2020-08-22 16:57:41 +0300 |
| commit | 31abc2bf0e8869db0a623c5a8c7a9ee24908678b (patch) | |
| tree | a73264e44300f1fc03dfcc082fbb80b57d9124af /src | |
| parent | feat(spi): implement SPI master #33 (diff) | |
| download | avr8js-31abc2bf0e8869db0a623c5a8c7a9ee24908678b.tar.gz avr8js-31abc2bf0e8869db0a623c5a8c7a9ee24908678b.tar.bz2 avr8js-31abc2bf0e8869db0a623c5a8c7a9ee24908678b.zip | |
style(spi): remove redundant eslint comments
Diffstat (limited to '')
| -rw-r--r-- | src/peripherals/spi.ts | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/peripherals/spi.ts b/src/peripherals/spi.ts index 0c02b95..0c03c3f 100644 --- a/src/peripherals/spi.ts +++ b/src/peripherals/spi.ts @@ -10,7 +10,6 @@ export interface SPIConfig { SPDR: u8; } -/* eslint-disable @typescript-eslint/no-unused-vars */ // Register bits: const SPCR_SPIE = 0x80; // SPI Interrupt Enable const SPCR_SPE = 0x40; // SPI Enable @@ -25,7 +24,6 @@ const SPSR_SPR_MASK = SPCR_SPR1 | SPCR_SPR0; const SPSR_SPIF = 0x80; // SPI Interrupt Flag const SPSR_WCOL = 0x40; // Write COLlision Flag const SPSR_SPI2X = 0x1; // Double SPI Speed Bit -/* eslint-enable @typescript-eslint/no-unused-vars */ export const spiConfig: SPIConfig = { spiInterrupt: 0x22, |