1 files changed, 18 insertions, 8 deletions
diff --git a/src/peripherals/eeprom.ts b/src/peripherals/eeprom.ts
index 0301701..bc386ca 100644
--- a/src/peripherals/eeprom.ts
+++ b/src/peripherals/eeprom.ts
@@ -1,6 +1,5 @@
-import { CPU } from '../cpu/cpu';
-import { avrInterrupt } from '../cpu/interrupt';
-import { u8, u16, u32 } from '../types';
+import { AVRInterruptConfig, CPU } from '../cpu/cpu';
+import { u16, u32, u8 } from '../types';
 
 export interface EEPROMBackend {
   readMemory(addr: u16): u8;
@@ -71,6 +70,16 @@ export class AVREEPROM {
 
   private writeCompleteCycles = 0;
 
+  // Interrupts
+  private EER: AVRInterruptConfig = {
+    address: this.config.eepromReadyInterrupt,
+    flagRegister: this.config.EECR,
+    flagMask: EEPE,
+    enableRegister: this.config.EECR,
+    enableMask: EERIE,
+    constant: true,
+  };
+
   constructor(
     private cpu: CPU,
     private backend: EEPROMBackend,
@@ -81,6 +90,10 @@ export class AVREEPROM {
 
       const addr = (this.cpu.data[EEARH] << 8) | this.cpu.data[EEARL];
 
+      if (eecr & EERE) {
+        this.cpu.clearInterrupt(this.EER);
+      }
+
       if (eecr & EEMPE) {
         this.writeEnabledCycles = this.cpu.cycles + 4;
       }
@@ -132,16 +145,13 @@ export class AVREEPROM {
   }
 
   tick() {
-    const { EECR, eepromReadyInterrupt } = this.config;
+    const { EECR } = this.config;
 
     if (this.writeEnabledCycles && this.cpu.cycles > this.writeEnabledCycles) {
       this.cpu.data[EECR] &= ~EEMPE;
     }
     if (this.writeCompleteCycles && this.cpu.cycles > this.writeCompleteCycles) {
-      this.cpu.data[EECR] &= ~EEPE;
-      if (this.cpu.interruptsEnabled && this.cpu.data[EECR] & EERIE) {
-        avrInterrupt(this.cpu, eepromReadyInterrupt);
-      }
+      this.cpu.setInterruptFlag(this.EER);
     }
   }
 }