avr8js - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Collapse)	Author	Files	Lines
2025-02-11	docs: add copyright notice to source code	Uri Shaked	1	-1/+4

2025-02-11	test: migrate tests from jest to vitest	Uri Shaked	1	-1/+2

2022-02-07	style(instruction.spec): add comments for missing instruction tests and ↵	Dudeplayz	1	-33/+103
	reorder tests according to the AVR datasheet
2022-02-07	test(instruction): add ADD, SUB and WDR unit tests	Dudeplayz	1	-0/+54

2020-09-30	fix(cpu): incorrect address for RAMPZ / EIND	Uri Shaked	1	-2/+2
	We used their I/O space address intead of their data space address. close #61
2020-09-02	fix(instruction): EICALL is broken	Uri Shaked	1	-0/+1
	close #59
2020-06-04	test(instruction): extract constants	Uri Shaked	1	-238/+274
	This makes the test code easier to follow
2020-04-28	fix(instruction): LD, ST instructions should take 2 clock cycles	Uri Shaked	1	-14/+14
	close #39
2020-04-09	feat(instruction): 22-bit PC support #31	Uri Shaked	1	-8/+73
	adapt CALL, ICALL, RCALL, RET, and RETI for MCUs with 22-bit PC
2020-04-09	feat(instruction): implement EICALL, EIJMP #31	Uri Shaked	1	-0/+23

2020-04-08	feat(instruction): implement ELPM #31	Uri Shaked	1	-0/+50

2020-04-02	test(instruction): use assembly in tests	Uri Shaked	1	-89/+91
	Refactored the tests to use AVR assembly instead of hardcoded bytecode. This change should make the tests much easier to read and maintain. Before: loadProgram('659a'); Now: loadProgram('SBI 0x0c, 5');
2020-03-22	refactor: added peripherals and cpu feature folders	lironh	1	-0/+0

2020-01-30	test(instruction): fix incorrect opcode in tests	Uri Shaked	1	-1/+1

2019-11-27	fix: SP not initialized on reset	Uri Shaked	1	-0/+8
	close #2
2019-11-20	test: SWAP, STS	Uri Shaked	1	-1/+19

2019-11-20	fix: SREG issues in ADC, CPC, SBC, SBCI	Uri Shaked	1	-1/+46
	also added regression test cases
2019-11-20	feat: implement most instructions	Uri Shaked	1	-0/+152

2019-11-20	feat: LPM, LSR, MOV, MOVW, MUL, MULS, MULSU, NEG	Uri Shaked	1	-9/+144
	+ tests
2019-11-20	feat: LAC, LAS, LAT, LDS instructions + tests	Uri Shaked	1	-0/+48

2019-11-20	feat: more instructions	Uri Shaked	1	-1/+62
	implement ADC, ADD, ADIW, AND, ANDI, ASR, BCLR, BLD, BRBC, BRBS, test some of them
2019-11-19	feat: CALL, INC, RET, RETI, ROR instructions	Uri Shaked	1	-9/+70

2019-11-19	feat: LDY/LDZ/LDDY/LDDZ instructions + tests	Uri Shaked	1	-7/+95

2019-11-19	feat: STY/STZ/STDY/STDZ instructions + tests	Uri Shaked	1	-2/+90

2019-11-19	feat: implement LDX instructions	Uri Shaked	1	-2/+35

2019-11-19	test: sort instructions by name	Uri Shaked	1	-19/+19

2019-11-19	feat: implement STX	Uri Shaked	1	-2/+24

2019-11-19	feat: implement some AVR instructions + tests	Uri Shaked	1	-0/+78