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path: root/src/cpu/instruction.spec.ts (follow)
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* docs: add copyright notice to source codeUri Shaked2025-02-111-1/+4
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* test: migrate tests from jest to vitestUri Shaked2025-02-111-1/+2
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* style(instruction.spec): add comments for missing instruction tests and ↵Dudeplayz2022-02-071-33/+103
| | | | reorder tests according to the AVR datasheet
* test(instruction): add ADD, SUB and WDR unit testsDudeplayz2022-02-071-0/+54
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* fix(cpu): incorrect address for RAMPZ / EINDUri Shaked2020-09-301-2/+2
| | | | | | We used their I/O space address intead of their data space address. close #61
* fix(instruction): EICALL is brokenUri Shaked2020-09-021-0/+1
| | | | close #59
* test(instruction): extract constantsUri Shaked2020-06-041-238/+274
| | | | This makes the test code easier to follow
* fix(instruction): LD, ST instructions should take 2 clock cyclesUri Shaked2020-04-281-14/+14
| | | | close #39
* feat(instruction): 22-bit PC support #31Uri Shaked2020-04-091-8/+73
| | | | adapt CALL, ICALL, RCALL, RET, and RETI for MCUs with 22-bit PC
* feat(instruction): implement EICALL, EIJMP #31Uri Shaked2020-04-091-0/+23
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* feat(instruction): implement ELPM #31Uri Shaked2020-04-081-0/+50
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* test(instruction): use assembly in testsUri Shaked2020-04-021-89/+91
| | | | | | | | | | | | Refactored the tests to use AVR assembly instead of hardcoded bytecode. This change should make the tests much easier to read and maintain. Before: loadProgram('659a'); Now: loadProgram('SBI 0x0c, 5');
* refactor: added peripherals and cpu feature folderslironh2020-03-221-0/+837