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3 daysavr32dd20 compat, onSleep hookHEADmainavr32dd20Apexo1-26/+27
2026-02-14style: organize importsUri Shaked1-1/+1
Also remove unused eslint-disable directives
2025-02-11docs: add copyright notice to source codeUri Shaked1-0/+3
2025-02-11chore(deps): upgrade prettierUri Shaked1-4/+4
reformat all code with the new prettier version
2021-09-10refactor: remove the ICPU interfaceUri Shaked1-2/+2
Removing the interface simplifies the code
2021-09-10feat(watchdog): implement watchdog timer #106Uri Shaked1-1/+1
2021-09-07fix(gpio): CBI/SBI handling in writes to PIN register #103Uri Shaked1-2/+4
fix #103
2020-09-30fix(cpu): incorrect address for RAMPZ / EINDUri Shaked1-6/+6
We used their I/O space address intead of their data space address. close #61
2020-09-02fix(instruction): EICALL is brokenUri Shaked1-1/+2
close #59
2020-04-29fix(timer): Reading TCNT in 2-cycle instructionsUri Shaked1-12/+12
close #40
2020-04-28fix(instruction): LD, ST instructions should take 2 clock cyclesUri Shaked1-6/+19
close #39
2020-04-09feat(instruction): 22-bit PC support #31Uri Shaked1-10/+30
adapt CALL, ICALL, RCALL, RET, and RETI for MCUs with 22-bit PC
2020-04-09feat(instruction): implement EICALL, EIJMP #31Uri Shaked1-0/+15
2020-04-08feat(instruction): implement ELPM #31Uri Shaked1-0/+21
2020-03-22refactor: added peripherals and cpu feature folderslironh1-1/+1
2020-03-18style(cpu): relocate some stray commentsUri Shaked1-4/+4
2020-03-18Move first comment inside functiongfeun1-1/+1
2020-03-18Optimize opcode checkgfeun1-372/+186
2019-12-01feat: add benchmarking codeUri Shaked1-15/+15
2019-11-20fix: SREG issues in ADC, CPC, SBC, SBCIUri Shaked1-9/+6
also added regression test cases
2019-11-20feat: implement most instructionsUri Shaked1-113/+303
2019-11-20feat: LPM, LSR, MOV, MOVW, MUL, MULS, MULSU, NEGUri Shaked1-10/+51
+ tests
2019-11-20feat: LAC, LAS, LAT, LDS instructions + testsUri Shaked1-4/+18
2019-11-20feat: more instructionsUri Shaked1-14/+78
implement ADC, ADD, ADIW, AND, ANDI, ASR, BCLR, BLD, BRBC, BRBS, test some of them
2019-11-19feat: CALL, INC, RET, RETI, ROR instructionsUri Shaked1-5/+36
2019-11-19doc: avr8js → AVR8jsUri Shaked1-1/+1
2019-11-19feat: LDY/LDZ/LDDY/LDDZ instructions + testsUri Shaked1-15/+47
2019-11-19feat: STY/STZ/STDY/STDZ instructions + testsUri Shaked1-10/+33
2019-11-19feat: implement LDX instructionsUri Shaked1-7/+15
2019-11-19doc: add opcode next to each instructionUri Shaked1-95/+95
2019-11-19feat: implement STXUri Shaked1-2/+5
2019-11-19doc: add some commentsUri Shaked1-0/+8
2019-11-19feat: implement some AVR instructions + testsUri Shaked1-0/+501
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-31 14:37:32 +0000