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path: root/src/cpu/instruction.ts (unfollow)
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2021-09-07fix(gpio): CBI/SBI handling in writes to PIN register #103Uri Shaked1-2/+4
2020-09-30fix(cpu): incorrect address for RAMPZ / EINDUri Shaked1-6/+6
2020-09-02fix(instruction): EICALL is brokenUri Shaked1-1/+2
2020-04-29fix(timer): Reading TCNT in 2-cycle instructionsUri Shaked1-12/+12
2020-04-28fix(instruction): LD, ST instructions should take 2 clock cyclesUri Shaked1-6/+19
2020-04-09feat(instruction): 22-bit PC support #31Uri Shaked1-10/+30
2020-04-09feat(instruction): implement EICALL, EIJMP #31Uri Shaked1-0/+15
2020-04-08feat(instruction): implement ELPM #31Uri Shaked1-0/+21
2020-03-22refactor: added peripherals and cpu feature folderslironh1-1/+1
2020-03-18style(cpu): relocate some stray commentsUri Shaked1-4/+4
2020-03-18Move first comment inside functiongfeun1-1/+1
2020-03-18Optimize opcode checkgfeun1-372/+186
2019-12-01feat: add benchmarking codeUri Shaked1-15/+15
2019-11-20fix: SREG issues in ADC, CPC, SBC, SBCIUri Shaked1-9/+6
2019-11-20feat: implement most instructionsUri Shaked1-113/+303
2019-11-20feat: LPM, LSR, MOV, MOVW, MUL, MULS, MULSU, NEGUri Shaked1-10/+51
2019-11-20feat: LAC, LAS, LAT, LDS instructions + testsUri Shaked1-4/+18
2019-11-20feat: more instructionsUri Shaked1-14/+78
2019-11-19feat: CALL, INC, RET, RETI, ROR instructionsUri Shaked1-5/+36
2019-11-19doc: avr8js → AVR8jsUri Shaked1-1/+1
2019-11-19feat: LDY/LDZ/LDDY/LDDZ instructions + testsUri Shaked1-15/+47
2019-11-19feat: STY/STZ/STDY/STDZ instructions + testsUri Shaked1-10/+33
2019-11-19feat: implement LDX instructionsUri Shaked1-7/+15
2019-11-19doc: add opcode next to each instructionUri Shaked1-95/+95
2019-11-19feat: implement STXUri Shaked1-2/+5
2019-11-19doc: add some commentsUri Shaked1-0/+8
2019-11-19feat: implement some AVR instructions + testsUri Shaked1-0/+501