| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | fix(cpu): incorrect address for RAMPZ / EIND | Uri Shaked | 2020-09-30 | 1 | -6/+6 |
| | | | | | | | We used their I/O space address intead of their data space address. close #61 | ||||
| * | fix(instruction): EICALL is broken | Uri Shaked | 2020-09-02 | 1 | -1/+2 |
| | | | | | close #59 | ||||
| * | fix(timer): Reading TCNT in 2-cycle instructions | Uri Shaked | 2020-04-29 | 1 | -12/+12 |
| | | | | | close #40 | ||||
| * | fix(instruction): LD, ST instructions should take 2 clock cycles | Uri Shaked | 2020-04-28 | 1 | -6/+19 |
| | | | | | close #39 | ||||
| * | feat(instruction): 22-bit PC support #31 | Uri Shaked | 2020-04-09 | 1 | -10/+30 |
| | | | | | adapt CALL, ICALL, RCALL, RET, and RETI for MCUs with 22-bit PC | ||||
| * | feat(instruction): implement EICALL, EIJMP #31 | Uri Shaked | 2020-04-09 | 1 | -0/+15 |
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| * | feat(instruction): implement ELPM #31 | Uri Shaked | 2020-04-08 | 1 | -0/+21 |
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| * | refactor: added peripherals and cpu feature folders | lironh | 2020-03-22 | 1 | -0/+726 |
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