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2020-05-04fix(timer): stop Timer 2 when all CS bits are 0Uri Shaked1-1/+1
close #44
2020-04-29fix(timer): Reading TCNT in 2-cycle instructionsUri Shaked2-4/+23
close #40
2020-04-28fix(timer): incorrect high counter byte behaviorUri Shaked2-46/+89
According to the datasheet, the value of the high byte of the counter for 16-bit timers (such as timer 1) is only updated when the low byte is being read/written. close #37
2020-04-27style: reformat code with prettier 2.xUri Shaked6-27/+27
prettier rules have changed since we upgraded to 2.x
2020-04-27fix(timer): Timer value should not increment on the same cycle as TCNTn writeUri Shaked2-2/+48
close #36
2020-04-12test(timer): add more 16-bit timer testsUri Shaked2-13/+56
also fix some issues found by @gfeun and the tests
2020-04-12feat(timer): implement 16-bit timersUri Shaked2-24/+148
e.g. Timer/Counter1 on ATmega328
2020-04-02fix: GPIO port listeners not invoked when writing to DDR registersUri Shaked2-3/+17
close #28
2020-03-22refactor: added peripherals and cpu feature folderslironh8-0/+1566
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