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	Commit message (Collapse)	Author	Files	Lines
2020-05-10	feat(gpio): add setPin() function	Uri Shaked	2	-0/+43
	close #26
2020-05-04	fix(timer): stop Timer 2 when all CS bits are 0	Uri Shaked	1	-1/+1
	close #44
2020-04-29	fix(timer): Reading TCNT in 2-cycle instructions	Uri Shaked	2	-4/+23
	close #40
2020-04-28	fix(timer): incorrect high counter byte behavior	Uri Shaked	2	-46/+89
	According to the datasheet, the value of the high byte of the counter for 16-bit timers (such as timer 1) is only updated when the low byte is being read/written. close #37
2020-04-27	style: reformat code with prettier 2.x	Uri Shaked	6	-27/+27
	prettier rules have changed since we upgraded to 2.x
2020-04-27	fix(timer): Timer value should not increment on the same cycle as TCNTn write	Uri Shaked	2	-2/+48
	close #36
2020-04-12	test(timer): add more 16-bit timer tests	Uri Shaked	2	-13/+56
	also fix some issues found by @gfeun and the tests
2020-04-12	feat(timer): implement 16-bit timers	Uri Shaked	2	-24/+148
	e.g. Timer/Counter1 on ATmega328
2020-04-02	fix: GPIO port listeners not invoked when writing to DDR registers	Uri Shaked	2	-3/+17
	close #28
2020-03-22	refactor: added peripherals and cpu feature folders	lironh	8	-0/+1566