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* fix(instruction): EICALL is brokenUri Shaked2020-09-022-1/+3
* style(spi): remove redundant eslint commentsUri Shaked2020-08-221-2/+0
* feat(spi): implement SPI master #33Uri Shaked2020-08-224-1/+368
* test(eeprom): remove useless lineUri Shaked2020-08-221-1/+0
* fix(timer): keeps counting even when stopped #41Uri Shaked2020-08-012-36/+51
* test(timer): use TestProgramRunnerUri Shaked2020-08-013-135/+128
* fix(eeprom): EEPROM write fails after first attemptUri Shaked2020-07-162-1/+33
* feat(eeprom): implement EEPROM peripheralUri Shaked2020-07-166-42/+408
* test(timer): remove stray console.logUri Shaked2020-07-161-1/+0
* test(twi): extract constantsUri Shaked2020-07-161-31/+46
* fix(usart): bitsPerChar looking at the wrong registerUri Shaked2020-07-092-7/+10
* fix(usart): TXC interrupt triggered incorrectlyUri Shaked2020-07-092-4/+18
* test(usart): extract constantsUri Shaked2020-07-091-49/+68
* test(instruction): extract constantsUri Shaked2020-06-041-238/+274
* test(timer): extract constantsUri Shaked2020-05-301-133/+185
* fix(gpio): port state not updated on DDR writeUri Shaked2020-05-292-0/+15
* perf(timer): improve tick() performanceUri Shaked2020-05-251-3/+4
* feat(timer): Compare Match Output (#45)Uri Shaked2020-05-254-57/+342
* feat(gpio): add setPin() functionUri Shaked2020-05-102-0/+43
* fix(timer): stop Timer 2 when all CS bits are 0Uri Shaked2020-05-041-1/+1
* fix(timer): Reading TCNT in 2-cycle instructionsUri Shaked2020-04-293-16/+35
* fix(timer): incorrect high counter byte behaviorUri Shaked2020-04-283-46/+97
* fix(instruction): LD, ST instructions should take 2 clock cyclesUri Shaked2020-04-282-20/+33
* style: reformat code with prettier 2.xUri Shaked2020-04-279-34/+34
* fix(timer): Timer value should not increment on the same cycle as TCNTn writeUri Shaked2020-04-272-2/+48
* test(timer): add more 16-bit timer testsUri Shaked2020-04-122-13/+56
* feat(timer): implement 16-bit timersUri Shaked2020-04-122-24/+148
* feat(instruction): 22-bit PC support #31Uri Shaked2020-04-094-20/+120
* feat(instruction): implement EICALL, EIJMP #31Uri Shaked2020-04-092-0/+38
* feat(instruction): implement ELPM #31Uri Shaked2020-04-082-0/+71
* fix: GPIO port listeners not invoked when writing to DDR registersUri Shaked2020-04-022-3/+17
* test(instruction): use assembly in testsUri Shaked2020-04-021-89/+91
* refactor: added peripherals and cpu feature folderslironh2020-03-2215-25/+25
* style(cpu): relocate some stray commentsUri Shaked2020-03-181-4/+4
* Move first comment inside functiongfeun2020-03-181-1/+1
* Optimize opcode checkgfeun2020-03-181-372/+186
* feat(twi): proper interrupt support #10Uri Shaked2020-02-032-5/+20
* test(twi): add master TWI receive test #10Uri Shaked2020-02-031-1/+175
* test(twi): refactor assembly code to be shorterUri Shaked2020-02-031-16/+11
* test(twi): assembly code to test master transmit #10Uri Shaked2020-01-312-3/+199
* fix(assembler): BRBC/BRBS forward labels failUri Shaked2020-01-312-2/+10
* test(instruction): fix incorrect opcode in testsUri Shaked2020-01-301-1/+1
* test(assembler): add unit testsUri Shaked2020-01-302-52/+379
* feat: add a simple AVR assembler for use in testsUri Shaked2020-01-302-0/+983
* feat(twi): partial TWI master implementation #10Uri Shaked2020-01-303-0/+211
* fix(gpio): pinState() value incorrect in GPIO listenersUri Shaked2020-01-112-1/+16
* feat(gpio): add pinState() methodUri Shaked2020-01-083-4/+69
* refactor: tslint → eslintUri Shaked2019-12-075-10/+13
* feat(usart): add onLineTransmit callbackUri Shaked2019-12-072-0/+56
* test(usart): more USART testsUri Shaked2019-12-072-1/+57
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