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* test(instruction): extract constantsUri Shaked2020-06-041-238/+274
| | | | This makes the test code easier to follow
* test(timer): extract constantsUri Shaked2020-05-301-133/+185
| | | | This makes the test code easier to follow
* fix(gpio): port state not updated on DDR writeUri Shaked2020-05-292-0/+15
| | | | | | Calling `pinState()` inside a GPIO port listener returns incorrect values after changing DDR close #47
* perf(timer): improve tick() performanceUri Shaked2020-05-251-3/+4
| | | | reduce the number of calls to TIFR/TIMSK getters
* feat(timer): Compare Match Output (#45)Uri Shaked2020-05-254-57/+342
| | | | | The Compare Match Output bits are used to generate hardware PWM signals on selected MCU pins. This is also the mechanism used by Arduino's analogWrite() method. See #32 for more details
* feat(gpio): add setPin() functionUri Shaked2020-05-102-0/+43
| | | | close #26
* fix(timer): stop Timer 2 when all CS bits are 0Uri Shaked2020-05-041-1/+1
| | | | close #44
* fix(timer): Reading TCNT in 2-cycle instructionsUri Shaked2020-04-293-16/+35
| | | | close #40
* fix(timer): incorrect high counter byte behaviorUri Shaked2020-04-283-46/+97
| | | | | | According to the datasheet, the value of the high byte of the counter for 16-bit timers (such as timer 1) is only updated when the low byte is being read/written. close #37
* fix(instruction): LD, ST instructions should take 2 clock cyclesUri Shaked2020-04-282-20/+33
| | | | close #39
* style: reformat code with prettier 2.xUri Shaked2020-04-279-34/+34
| | | | prettier rules have changed since we upgraded to 2.x
* fix(timer): Timer value should not increment on the same cycle as TCNTn writeUri Shaked2020-04-272-2/+48
| | | | close #36
* test(timer): add more 16-bit timer testsUri Shaked2020-04-122-13/+56
| | | | also fix some issues found by @gfeun and the tests
* feat(timer): implement 16-bit timersUri Shaked2020-04-122-24/+148
| | | | e.g. Timer/Counter1 on ATmega328
* feat(instruction): 22-bit PC support #31Uri Shaked2020-04-094-20/+120
| | | | adapt CALL, ICALL, RCALL, RET, and RETI for MCUs with 22-bit PC
* feat(instruction): implement EICALL, EIJMP #31Uri Shaked2020-04-092-0/+38
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* feat(instruction): implement ELPM #31Uri Shaked2020-04-082-0/+71
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* fix: GPIO port listeners not invoked when writing to DDR registersUri Shaked2020-04-022-3/+17
| | | | close #28
* test(instruction): use assembly in testsUri Shaked2020-04-021-89/+91
| | | | | | | | | | | | Refactored the tests to use AVR assembly instead of hardcoded bytecode. This change should make the tests much easier to read and maintain. Before: loadProgram('659a'); Now: loadProgram('SBI 0x0c, 5');
* refactor: added peripherals and cpu feature folderslironh2020-03-2215-25/+25
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* style(cpu): relocate some stray commentsUri Shaked2020-03-181-4/+4
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* Move first comment inside functiongfeun2020-03-181-1/+1
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* Optimize opcode checkgfeun2020-03-181-372/+186
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* feat(twi): proper interrupt support #10Uri Shaked2020-02-032-5/+20
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* test(twi): add master TWI receive test #10Uri Shaked2020-02-031-1/+175
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* test(twi): refactor assembly code to be shorterUri Shaked2020-02-031-16/+11
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* test(twi): assembly code to test master transmit #10Uri Shaked2020-01-312-3/+199
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* fix(assembler): BRBC/BRBS forward labels failUri Shaked2020-01-312-2/+10
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* test(instruction): fix incorrect opcode in testsUri Shaked2020-01-301-1/+1
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* test(assembler): add unit testsUri Shaked2020-01-302-52/+379
| | | | fix some bugs found during unit tests
* feat: add a simple AVR assembler for use in testsUri Shaked2020-01-302-0/+983
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* feat(twi): partial TWI master implementation #10Uri Shaked2020-01-303-0/+211
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* fix(gpio): pinState() value incorrect in GPIO listenersUri Shaked2020-01-112-1/+16
| | | | fix #9
* feat(gpio): add pinState() methodUri Shaked2020-01-083-4/+69
| | | | close #8
* refactor: tslint → eslintUri Shaked2019-12-075-10/+13
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* feat(usart): add onLineTransmit callbackUri Shaked2019-12-072-0/+56
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* test(usart): more USART testsUri Shaked2019-12-072-1/+57
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* feat: add benchmarking codeUri Shaked2019-12-011-15/+15
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* feat: initial implementation of USARTUri Shaked2019-12-013-0/+180
| | | | #6
* fix: Wrong prescaler for Timer2Uri Shaked2019-11-302-6/+44
| | | | fix #5
* feat: Output Compare for TimersUri Shaked2019-11-302-6/+185
| | | | close #4
* feat: add more GPIO portsUri Shaked2019-11-302-1/+57
| | | | close #3
* fix: SP not initialized on resetUri Shaked2019-11-274-2/+28
| | | | close #2
* feat: GPIO peripheral implementationUri Shaked2019-11-254-2/+126
| | | | Add new AVRIOPort class, implements GPIO output logic
* feat: initial timer implementationUri Shaked2019-11-213-0/+232
| | | | | | | 8-bit timers basic functionality + tests: 1. basic counting + prescaler 2. timer overflow 3. timer overflow interrupt
* doc: add comment to interrupt.tsUri Shaked2019-11-211-0/+8
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* feat: implement avrInterrupt()Uri Shaked2019-11-213-0/+30
| | | | used to invoke hardware interrupt
* test: SWAP, STSUri Shaked2019-11-201-1/+19
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* fix: SREG issues in ADC, CPC, SBC, SBCIUri Shaked2019-11-202-10/+52
| | | | also added regression test cases
* feat: implement most instructionsUri Shaked2019-11-202-113/+455
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