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* refactor: central interrupt handling #38Uri Shaked2020-12-0912-92/+285
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* test(cpu): improve test nameUri Shaked2020-12-091-1/+1
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* fix(usart): respect the given baud rate #16Uri Shaked2020-11-272-54/+150
| | | | close #16
* feat(clock): Clock Prescale (CLKPR) support #68Uri Shaked2020-11-253-0/+185
| | | | close #68
* feat: Support for simulating ATtinyx5 (e.g. ATtiny85) timers #64Uri Shaked2020-11-142-12/+60
| | | | close #64
* fix: AVRTimerConfig interface not exported #65Uri Shaked2020-11-142-2/+8
| | | | close #65
* test(gpio): extract constantsUri Shaked2020-10-071-26/+30
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* fix(gpio): Changing pinMode from `INPUT` to `INPUT_PULLUP` doesn't trigger ↵Uri Shaked2020-10-072-4/+13
| | | | | | listeners close #62
* fix(cpu): incorrect address for RAMPZ / EINDUri Shaked2020-09-302-8/+8
| | | | | | We used their I/O space address intead of their data space address. close #61
* perf(timer): speed up interrupt handlingUri Shaked2020-09-021-1/+4
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* perf(timer): improve timer speedUri Shaked2020-09-022-11/+17
| | | | cache the value of the clock divider
* fix(interrupt): broken on ATmega2560Uri Shaked2020-09-022-1/+23
| | | | close #58
* fix(instruction): EICALL is brokenUri Shaked2020-09-022-1/+3
| | | | close #59
* style(spi): remove redundant eslint commentsUri Shaked2020-08-221-2/+0
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* feat(spi): implement SPI master #33Uri Shaked2020-08-224-1/+368
| | | | close #33
* test(eeprom): remove useless lineUri Shaked2020-08-221-1/+0
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* fix(timer): keeps counting even when stopped #41Uri Shaked2020-08-012-36/+51
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* test(timer): use TestProgramRunnerUri Shaked2020-08-013-135/+128
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* fix(eeprom): EEPROM write fails after first attemptUri Shaked2020-07-162-1/+33
| | | | close #54
* feat(eeprom): implement EEPROM peripheralUri Shaked2020-07-166-42/+408
| | | | close #15
* test(timer): remove stray console.logUri Shaked2020-07-161-1/+0
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* test(twi): extract constantsUri Shaked2020-07-161-31/+46
| | | | This makes the test code more readable
* fix(usart): bitsPerChar looking at the wrong registerUri Shaked2020-07-092-7/+10
| | | | close #52
* fix(usart): TXC interrupt triggered incorrectlyUri Shaked2020-07-092-4/+18
| | | | close #51
* test(usart): extract constantsUri Shaked2020-07-091-49/+68
| | | | This makes the test code easier to read
* test(instruction): extract constantsUri Shaked2020-06-041-238/+274
| | | | This makes the test code easier to follow
* test(timer): extract constantsUri Shaked2020-05-301-133/+185
| | | | This makes the test code easier to follow
* fix(gpio): port state not updated on DDR writeUri Shaked2020-05-292-0/+15
| | | | | | Calling `pinState()` inside a GPIO port listener returns incorrect values after changing DDR close #47
* perf(timer): improve tick() performanceUri Shaked2020-05-251-3/+4
| | | | reduce the number of calls to TIFR/TIMSK getters
* feat(timer): Compare Match Output (#45)Uri Shaked2020-05-254-57/+342
| | | | | The Compare Match Output bits are used to generate hardware PWM signals on selected MCU pins. This is also the mechanism used by Arduino's analogWrite() method. See #32 for more details
* feat(gpio): add setPin() functionUri Shaked2020-05-102-0/+43
| | | | close #26
* fix(timer): stop Timer 2 when all CS bits are 0Uri Shaked2020-05-041-1/+1
| | | | close #44
* fix(timer): Reading TCNT in 2-cycle instructionsUri Shaked2020-04-293-16/+35
| | | | close #40
* fix(timer): incorrect high counter byte behaviorUri Shaked2020-04-283-46/+97
| | | | | | According to the datasheet, the value of the high byte of the counter for 16-bit timers (such as timer 1) is only updated when the low byte is being read/written. close #37
* fix(instruction): LD, ST instructions should take 2 clock cyclesUri Shaked2020-04-282-20/+33
| | | | close #39
* style: reformat code with prettier 2.xUri Shaked2020-04-279-34/+34
| | | | prettier rules have changed since we upgraded to 2.x
* fix(timer): Timer value should not increment on the same cycle as TCNTn writeUri Shaked2020-04-272-2/+48
| | | | close #36
* test(timer): add more 16-bit timer testsUri Shaked2020-04-122-13/+56
| | | | also fix some issues found by @gfeun and the tests
* feat(timer): implement 16-bit timersUri Shaked2020-04-122-24/+148
| | | | e.g. Timer/Counter1 on ATmega328
* feat(instruction): 22-bit PC support #31Uri Shaked2020-04-094-20/+120
| | | | adapt CALL, ICALL, RCALL, RET, and RETI for MCUs with 22-bit PC
* feat(instruction): implement EICALL, EIJMP #31Uri Shaked2020-04-092-0/+38
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* feat(instruction): implement ELPM #31Uri Shaked2020-04-082-0/+71
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* fix: GPIO port listeners not invoked when writing to DDR registersUri Shaked2020-04-022-3/+17
| | | | close #28
* test(instruction): use assembly in testsUri Shaked2020-04-021-89/+91
| | | | | | | | | | | | Refactored the tests to use AVR assembly instead of hardcoded bytecode. This change should make the tests much easier to read and maintain. Before: loadProgram('659a'); Now: loadProgram('SBI 0x0c, 5');
* refactor: added peripherals and cpu feature folderslironh2020-03-2215-25/+25
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* style(cpu): relocate some stray commentsUri Shaked2020-03-181-4/+4
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* Move first comment inside functiongfeun2020-03-181-1/+1
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* Optimize opcode checkgfeun2020-03-181-372/+186
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* feat(twi): proper interrupt support #10Uri Shaked2020-02-032-5/+20
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* test(twi): add master TWI receive test #10Uri Shaked2020-02-031-1/+175
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