From 8fdcb01f16be55c1ff2d193ac97a14ea69e9c080 Mon Sep 17 00:00:00 2001
From: Uri Shaked
Date: Wed, 20 Nov 2019 22:55:54 +0200
Subject: test: SWAP, STS

---
 src/instruction.spec.ts | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

(limited to 'src/instruction.spec.ts')

diff --git a/src/instruction.spec.ts b/src/instruction.spec.ts
index 58cb33a..a63dc67 100644
--- a/src/instruction.spec.ts
+++ b/src/instruction.spec.ts
@@ -1,4 +1,4 @@
-import { CPU, ICPU } from './cpu';
+import { CPU } from './cpu';
 import { avrInstruction } from './instruction';
 
 describe('avrInstruction', () => {
@@ -676,6 +676,15 @@ describe('avrInstruction', () => {
     expect(cpu.cycles).toEqual(3);
   });
 
+  it('should execute `STS 0x151, r31` instruction', () => {
+    loadProgram('f0935101');
+    cpu.data[31] = 0x80; // r31 <- 0x80
+    avrInstruction(cpu);
+    expect(cpu.pc).toEqual(2);
+    expect(cpu.cycles).toEqual(2);
+    expect(cpu.data[0x151]).toEqual(0x80);
+  });
+
   it('should execute `ST X, r1` instruction', () => {
     loadProgram('1c92');
     cpu.data[1] = 0x5a; // r1 <- 0x5a
@@ -797,6 +806,15 @@ describe('avrInstruction', () => {
     expect(cpu.data[30]).toEqual(0x50); // verify that Z was unchanged
   });
 
+  it('should execute `SWAP r1` instruction', () => {
+    loadProgram('1294');
+    cpu.data[1] = 0xa5; // r1 <- 0xa5
+    avrInstruction(cpu);
+    expect(cpu.pc).toEqual(1);
+    expect(cpu.cycles).toEqual(1);
+    expect(cpu.data[1]).toEqual(0x5a); // r1
+  });
+
   it('should execute `XCH r21` instruction', () => {
     loadProgram('5493');
     cpu.data[21] = 0xa1; // r21 <- 0xa1
-- 
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